Giovanni De Micheli,  École Polytechnique Fédérale de Lausanne, Switzerland

Majority-based synthesis for digital nano-technologies 
Logic synthesis/optimization algorithms and tools have been used for over three decades. Still they suffer from various weaknesses, because they were conceived with CMOS AOI static gates in mind,  with more primitive computers and storage systems, and without a strong formal basis. The design of large-scale, computation oriented, digital circuits is still a main challenge even with state of the art commercial tools.  Because of the convergence of fabrication technologies, the competitive edge in CMOS design resides in its logic-level structuring achieved within synthesis. Moreover, novel nano technologies open new horizons by means of logic gates with enhanced functionality. Thus, more than ever, synthesis technology is a key to exploit technology in the search for the best design.   This talk shows the motivation for searching better models and algorithms –  as compared to the state of the art – for logic synthesis. A new Boolean algebra and model is shown to be effective for digital circuit optimization for speed, area and power consumption. Experimental results show that the new tool, MIGHTY, outperfoms a commercial tool on the three metrics after complete physical design.

Biography: Giovanni De Micheli is Professor and Director of the Institute of Electrical Engineering at EPFL. He is program leader of the Nano-Tera.ch program. Previously, he was Professor of Electrical Engineering at Stanford University.  Prof. De Micheli is a Fellow of ACM and IEEE and a member of the Academia Europaea.  He is author of: Synthesis and Optimization of Digital Circuits, McGraw-Hill, 1994, co-author and/or co-editor of eight other books and of over 600 technical articles. He is member of the Scientific Advisory Board of IMEC (Leuven, B), CfAED (Dresden, D) and STMicroelectronics. Prof. De Micheli is the recipient of the 2012 IEEE/CAS Mac Van Valkenburg award for contributions to theory, practice and experimentation in design methods and tools, of the 2003 IEEE Emanuel Piore Award for contributions to computer-aided synthesis of digital systems, and of other best paper awards.

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Luca Benini,  Eidgenössische Technische Hochschule Zürich (ETH Zurich), Switzerland

Toward energy-neutral computational sensing – challenges and opportunities

The  “internet of everything” envisions trillions of connected objects loaded with high-bandwidth sensors requiring massive amounts of local signal processing, fusion, pattern extraction and classification. Higher level intelligence, requiring local storage and complex search and matching algorithms, will come next, ultimately leading to situational awareness and truly “intelligent things” harvesting energy from their environment. From the computational viewpoint, the challenge is formidable and can be addressed only by pushing computing fabrics toward massive parallelism and brain-like energy efficiency levels. We believe that CMOS technology can still take us a long way toward this vision. Our recent results with the PULP (parallel ultra-low power) open computing platform demonstrate that pj/OP (GOPS/mW) computational efficiency is within reach in today’s 28nm CMOS FDSOI technology. In the longer term, looking toward the next 1000x of energy efficiency improvement,  we will need to fully exploit the flexibility of heterogeneous 3D integration,  stop being religious about analog vs. digital, Von Neumann vs. “new” computing paradigms, and seriously look into relaxing traditional “hardware-software contracts” such as numerical precision and error-free permanent storage.

Biography: Luca Benini is the chair of digital Circuits and systems at ETHZ and a Full Professor at the University of Bologna. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble. He has held  visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University. Dr. Benini’s research interests are in energy-efficient system design and Multi-Core SoC design.  He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member  of the Academia Europaea.

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Yuichi Nakamura, General Manager of Green Platform Labs., NEC, Japan. 

Social Value Creation Accelerated by MCSoC

In 2050, the earth would have 9.6 billion people, and demand 1.8 times energy and 1.5 times food and 1.6 times water as huge as it in 2015. Then, various social problems would be occurred in various areas, for example, crimes, luck of resources, broken of infrastructure and etc. In the cases, an integration of ICT (Information and Communication Technology) and “Big data” analysis is one of the good methods to solve such the problems. Since it takes long time to analyze complicated “Big data”, an efficient computer system is required and MCSoC is the best platform to solve complex problems. In this talk, several examples of social problems, and their solutions by using MCSoC are presented. In addition, the concept and applications of the vector processor, an example of MCSoC, which we developed, are introduced. I hope my talk would be a useful reference in the discussion of MCSoC applications from the practical viewpoints.

Biography: Yuichi Nakamura received his B.E. degree in information engineering and M.E. degree in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his PhD. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He joined NEC Corp. in 1988 and he is currently a general manager at Green platform Research Labs., NEC Corp. He is also a guest professor of National Institute of Informatics and a vice chair of IEEE CAS Japan Chapter. He has more than 25 years of professional experience in electronic design automation, network on chip, signal processing, and embedded software development.

Roberto_Zafalon

Roberto Zafalon, EU Technology Programmes Director, ST Microelectronics, Italy. 

Smart Systems: the key enabling technology for future IoT

The Internet of Things (IoT) refers to uniquely identifiable objects and their virtual representations in an Internet-like structure. Actually, the Internet of Things (IoT) is a vision evolving very fast to reality as it is under construction today. The stakeholders are known, the debate has yet to start. So what will really happen when things, homes and cities will become smart and data-interconnected? There are more “nomadic parts” to monitor, e.g. components, devices, applications, moving vehicles and systems. Indeed, a huge number of remotely distributed IoT nodes are already out there! …and they are increasing at a pace greater than 20% per year on average (e.g. by 2018 for the Factory of the Future the IoT will be worth 100 B$ (CAGR 20%); on digital signage it will be worth 28 B$ (CAGR 35%)). The potential attack area has increased by orders of magnitude. Even the hackers are more sophisticated and the hacks themselves are more pernicious. The key trends likely to play a part of IoT will be the increasing use of apps, machine-to-machine (M2M) and the Cloud. The Internet will be a fundamental force affecting the future of business. According to a report issued by Cisco, the number of connected devices (i.e. through IPv6 and evolution) will grow to 50 billion devices by 2020. The internet traffic will be close to 44 Zettabytes (i.e. 10^21 bytes). The result will probably be a Tsunami of what at first looks like very small steps or incremental changes. How to drive and anticipate a world where smart objects will surround us in smart homes and wearables, offices, streets, cars, hospitals, energy and water utilities, cities and farms? e.g. Do the car makers realize the impact of turning the modern automobile into a smartphone? Will the remote hackering of a Jeep Cherokee in the US, reported on July 2015, teach something to the automotive industry? The web shall not represent the pinnacle of the digital revolution, at all. Actually, pervasive Smart Systems will represent the largest portion of M2M platforms connected to the internet. In the domain of IoT, where devices, networks, smart systems and billions of people are all interconnected, issues like security, robustness and quality of service are much more complex. A Smart System consists of heterogeneous subsystems and components providing different functionalities; they are normally implemented as Multi-Core integrated platforms and very tiny Systems in Package (SiP). To fully exploit the potential of current nano-technologies, as well as to enable the integration of existing/new IPs and More than Moore devices, the capability to make smart system miniaturization and Multi-Chip in a Package implementation is necessary. Furthermore, such goals are only achievable if dedicated M2M interfaces and SW tools for smart subsystems/components design are available to designers and system integrators.

This talk offers an overview of the most innovative technology platforms under development and the major challenges faced by the industry when pursuing smart system design capabilities, discussing and motivating the user’s needs and the huge market opportunities unlashed by the Internet of Things.

Biography:Dr. Roberto Zafalon is EU Technology Programmes Director – Italy, in charge to foster and leverage the link between ST technology groups and the R&D cooperative EU programs. at STMicroelectronics, Agrate Brianza (Milano), Italy. In his current capacity since July 2007, he elaborates the vision and roadmap, seeks for project financing and drives industrial R&D teams to pursue innovative solutions in the field of embedded systems and nanoelectronics, for corporate product divisions and labs. He is with STMicroelectronics (one of world’s top 5 semiconductor firms) since 25 years. He is Steering Board member of ARTEMIS-IA and EPOSS (the European Technology Platform on Smart Systems Integration) and member of AENEAS working groups. He currently is, and has been in the past, General Project Manager and Coordinator of major Integrated Projects under FP6, FP7 and JTI calls 2009-2013, including KET Pilot Lines. He has been selected by FP7- ICT, ARTEMIS JU, H2020 FET and ECSEL as independent expert to review the project submitted to some past calls. During his carrier, Dr. Zafalon has been participating and leading several internal Task Forces and Special Action Groups at corporate level, addressing from Design Methodology, to Signal Integrity, to Low Power Design and Policy for IP Reuse. He has a large experience of managing and coordinating industrial and geographically distributed R&D teams, managing resources (i.e. people and budget) as well as international research projects, including European MEDEA+ and FP5, FP6, FP7 and H2020 research frameworks. He is member of the Steering Board of ARTEMIS-IA and EPOSS. As of today, he contributed to 82 international scientific publications so far, including Conferences, Journals/Transactions and Books. He holds 8 international patents, four European, three USA and one Japanese, in the field of low power design, processors and architectures. He has been a fellow member of the STMicroelectronics Patent Committee.