Prof. Ryuichi Oka, University of Aizu, Japan
Title: Field Computation Architecture of Algorithms for Intelligent and Smart Pattern Processing
Abstract: In my talk, we propose a scope called field computation architecture as a scheme of hardware implementation. In the real world, there are two types of information. One is pattern information such as time signal, two-dimensional image, video composed of time and the two-dimensional image. Pattern information has its own intrinsic neighborhood relation between elements. Another one is symbol information such as natural language, the network of words, list of symbols, etc. Each element of symbol information has its own intelligent meaning rather than an element of pattern information. We consider in this talk only the processing of pattern information. In the field of pattern processing, field computation is frequently used for extracting features of pattern like edge, line, corner, filtering using a mask, etc. However, the conventional field computation provides microscopic or low intelligent entity in most of the cases. These field computations are regarded as a kind of pre-processing of the pattern. Then main algorithms including symbol processing are devised for final intelligent results by using the results of pre-processing. We focus on field computation algorithms realizing intelligent and smart pattern processing. In this talk, we show five algorithms and their smart functions and experimental results as references for considering new hardware architecture.
Biography: Dr. Ryuichi Oka graduated from a master course in mathematical engineering, University of Tokyo, Japan, March 1970 and worked for Electrotechnical Laboratory of Ministry and Industry and Trade from April 1970 as a researcher and received Dr. degree of engineering (1984) from The University of Tokyo. He stayed at National Research Council of Canada as a visiting scientist (July 1984 — June 1985). He worked for a ten-year national project of Japan called Real World Computing (March 1993 – March 2002) as a director of the division and a chief of the laboratory. His research areas include character recognition, speech recognition and retrieval, image retrieval, image processing, image understanding, computer vision (3D scene reconstruction from a video), data mining, data visualization, and mobile robot, drone network connected by cables, etc. He proposed a family of so-called Continuous Dynamic Programming for segmentation-free optimal matching between two sequence patterns, two two-dimensional patterns, two three dimensional patterns and two time-space patterns. These matching methods are widely used for researchers and making industrial products.
Prof. Chong-Min Kyung, Korea Advanced Institute of Science and Technology, South Korea
Title: Rolling up Asia Vision Through Intertwining Research and Business Development (R&BD) Around Smart Sensor Systems Technology
Abstract: In this talk, I like to discuss the future prospect and vision of Asian business and research ecosystem rolled up through the role of smart sensors and systems, i.e., smart sensor systems. The journey of information as one crucial axis of human society, from the moment of sensing to targeted service, is served by a large variety of storage, processing, communication/networking and energy saving/harvesting technology. The mode of interaction of the involved techniques is so complex and dynamic, that the necessity of sharing a holistic view and handling of all research and business-related activities together seems now unquestionable. This talk proposes to start forming an environment for intertwined R&BD in this region of the globe, Asia where both problems and solutions exist dormant but in abundance.
Biography: Chong-Min Kyung received B.S. in EE from Seoul National University in 1975, M.S. and Ph.D. in EE from KAIST in 1977 and 1981, respectively. He joined KAIST in 1983 and has been working on CAD algorithms, 3-D graphics, and System-on-a-Chip design including RISC/CISC microprocessors, VLIW and reconfigurable DSP cores. His current research includes system-level low-power design, electrical/thermal co-design in 3D IC, and especially cost-energy-rate-distortion optimization. He is founding Director of the IDEC (Integrated Circuit Design Education Center), and currently leads Center for Integrated Smart Sensors, funded as Global Frontier Project by Korean Government as a national initiative for developing various smart sensors covering bio/health, vehicular, and environmental applications. He received numerous awards in international conferences including ASP-DAC 1997 and 1998, Best Paper Awards in DAC in 2000, ICSPAT in 1999, ICCD in 1999, and ISQED in 2014. In 2000, he received National Medal from Korean government for his contribution to research and education in IC design. He is a member of National Academy of Engineering Korea and Korean Academy of Science and Technology. He is IEEE fellow.
Prof. Hans G. Kerkhoff, University of Twente, Netherlands
Title: How to Guarantee High Dependability of Future Many-Core Systems-on-Chip
Abstract: The tremendous developments in semiconductor technology, resulting in a downscaling up to 7nm currently, have enabled the integration of large numbers of processor cores in Systems-on-Chip. Unfortunately, this has also a negative influence on the dependability of MC-SoCs, of which NASA indicated since the 65nm node the dramatic influence on the attribute reliability and hence lifetime of such systems. Especially in demanding safety-critical applications under harsh environments, such as in space and automotive, this life time can be far less than the normally guaranteed lifetime of the system; for instance for cars 10 years is considered as a normal lifetime. One approach to solve this issue can be to very carefully design the processors (and other electronics) under worst-case conditions, having as disadvantages a much larger design time and costs, and probably less performance. Another alternative can be the periodic (scan) test of each processor during life time, for instance via a dependability manager, which is basically a BIST solution, and subsequently deactivate the faulty processor while activating remaining processing resources (run-time mapping). The disadvantage of this approach is that the down-time can be significant. A recent very promising technique uses IJTAG-compatible embedded instruments which are monitoring environmental conditions as well as aging and performance parameters of cores, which are on-chip and on-line, providing data with regard to the degrading processes in a core. Via (software) data fusion and life-time prediction, a core can be (electronically) disconnected from the system and activate new resources without any down time. The talk will include all the above issues, illustrated by implementations and measurement results.
Biography: Hans G. Kerkhoff received his M.Sc. degree in Telecommunication with honours at the Technical University of Delft in 1977, the Netherlands. In the same year he became staff member of the chair IC-Technology & Electronics at the Faculty of EE, University of Twente in Enschede, the Netherlands. He obtained a Ph.D. in Technical Science (micro-electronics) at the University of Twente in 1984. In the same year he was appointed associate professor in Testable Design and Testing (TDT) at the Faculty of EE at the University of Twente. In 1991, he became head of the research group TDT of the MESA+ Research Institute (for Nanotechnology) and headed the MESA Test Centre (MTC). In 1992 he spent his sabbatical year at the test company Advantest in Silicon Valley, USA. From 1995 up to 1999, he worked in addition part-time at the Philips Research Laboratories in the VLSI Design and Test Group at Eindhoven. In 2000, he founded the company TwenTest, specializing in consultancy in the area of testable design and test of dependable mixed-signal microsystems. Currently he is with the Centre of Telematics and Information Technology (CTIT), the largest research institute of the University of Twente, heading the CAES-TDT group and responsible for Hardware Dependability of Systems-on-Silicon. He advised 26 Ph.D. students in this research area and has (co-) authored over 330 publications. He is and has been involved in many national (STW, FOM) and European (FP3-FP7, MEDEA, MEDEA+, Catrene, ENIAC, Horizon 2020) scientific projects.
Prof. Van Tam Nguyen, Telecom ParisTech & INTEK
Title: Cognitive Computation and Communication: A Complement Solution to Cloud for IoT
Abstract: The Internet of Thing (IoT) is experiencing explosive growth in the number of devices and applications. However, the existing cloud-centric architecture of IoT poses serious challenges regarding network latency, privacy, and energy-efficiency. We have presented COGNICOM+ concept, a brain-inspired software-hardware paradigm, to support IoT’s future growth and developed 4 research directions – flexible radio, convolutional neural network accelerator, compressed deep learning, and game theory for reasoning and collaboration – within COGNICOM+. The key idea is to bring computing closer to the end-user while focusing on optimal uses of local smart application gateway and cloud computing. COGNICOM+ consists of two key components: Cognitive Engine (CE) and Smart Connectivity (SC). The cognitive engine is powered by deep-learning algorithms integrated with game-theoretic decision analytics, implemented on a low-power application-specific integrated circuit. It provides cognitive functions to smart objects. The smart connectivity integrates neural network inspired designs of cognitive radio, transceivers, and baseband processors. The SC provides flexible and reliable connections to IoT objects and optimally distributes communication resources.
Biography: Van Tam Nguyen was born in Tinh Gia, Thanh Hoa, Vietnam in 1975. He received the Diplôme d’Ingenieur from Ecole Superieure d’Electricite (Supelec), a M.Sc. degree in automatic and signal processing from University Paris XI and graduated in image processing from EPFL, Switzerland in 2000, a Ph.D. degree in Communications and Electronic from Ecole Nationnale Superieure des Telecommunications (Telecom ParisTech) in 2004 and a HDR from University Paris VI in 2016. From 2000 to 2005 he worked mainly on Euro- pean Project SPRING (Scientific Multidisciplinary Network for metering – IST-1999- 12342) with Schlumberger and Ecole Nationale Superieure des Telecommunications. Since 2005, he has been on the faculty of Telecom ParisTech, where he is currently an Associate Professor (on leave) in the Communications and Electronic Department. In 2015 and 2016, he was a Senior Marie Curie Fellow at UC Berkeley. He held visiting positions at the University of Aizu, Japan in 2012 and UC Berkeley in 2013 and 2014. He was also a rank A guest researcher of NICT, Japan, from 2012 July to 2013 June, where he has proposed a surveillance game for the reliability and worked on radio resource management for cognitive radio systems. He was a Visiting Associate Professor from July 2016 to December 2017. At UC Berkeley and Stanford, he has proposed and designed ”COGNICOM” concept, a brain-inspired software-hardware paradigm, to support IoT’s future growth. COGNICOM brings computing closer to end-user and focuses on optimal uses of local Smart Application Gateway and cloud computing. COGNICOM consists of two key components: Cognitive Engine and Smart Connectivity. The cognitive engine is powered by deep-learning algorithms integrated with game-theoretic decision analytics, implemented on low-power Network Multi- Processor System on Chip. The cognitive engine provides cognitive functions (e.g. anomaly detection and decision making) to smart objects. SC integrates neural network inspired designs of cognitive radio, transceivers and baseband processors. The smart connectivity provides flexible and reliable connections to IoT objects and optimally distributes communication resources. The designs of both cognitive engine and smart connectivity will leverage his past success in designing cognitive radios and surveillance game.
Since 2018, he has been the CEO of INTEK (Institute of Applied Technology) – www.intek.io