Power-Aware Testing for Low-Power VLSI Circuits

Xiaoqing Wen, Kyushu Institute of Technology, Japan

Abstract: Low-power VLSI circuits are indispensable for all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven IoT systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false timing failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research directions in this field will also be discussed.

Bio: Xiaoqing WEN received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. He was an Assistant Professor with Akita University, Japan, from1993 to 1997, and a Visiting Researcher with the University of Wisconsin–Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc., USA, in 1998, and served as its Vice President and Chief Technology Officer until 2003. He joined Kyushu Institute of Technology, Japan, in 2003, where he is currently a Professor of the Department of Computer Science and Networks. He founded Dependable Integrated Systems Research Center at Kyushu Institute of Technology in 2013 and served as its Director until 2015. He is a Co-Founder and Co-Chair of the Technical Activity Committee on Power-Aware Testing under Test Technology Technical Council (TTTC) of IEEE Computer Society. He is an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Journal of Electronic Testing: Theory and Applications (JETTA). He co-authored and co-edited the latest VLSI test textbook (VLSI Test Principles and Architectures: Design for Testability) in 2006 and the first comprehensive book on power-aware VLSI testing (Power-Aware Testing and Test Strategies for Low Power Devices) in 2009. His research interests include design, test, and diagnosis of VLSI circuits. He has published more than 200 peer-reviewed papers and has conducted 19 tutorials on low-power VLSI testing. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Information Systems Society (ISS) of the Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE, a Senior Member of Information Processing Society of Japan (IPSJ), and a Senior Member of IEICE. (http://aries3a.cse.kyutech.ac.jp/~wen)

***Three to four other outstanding KN speakers from Academia and Industry will be added here soon.