Luca Benini, University of Bologna, Italy

Near-threshold Parallel Computing in a mW Power Envelope: How and Why?
With the widespread diffusion of distributed, wearable visual scene understanding and sensor fusion, the bar for ultra-low power scalable processing is set to brain-like energy efficiency levels. I will give an an overview of the PULP  (Parallel processing Ultra-Low Power platform),  an architecture built on clusters of tightly-coupled OpenRISC ISA cores, with advanced techniques for fast performance and energy scalability that aggressively exploit the potential of UTB FDSOI 28nm technology. PULP performance can be scaled over a 1x-354x range, with a peak   performance/power efficiency  close to  0.25 GOPS/W.  Finally, I will discuss ideas in near-threshold parallel processing which will make it possible to break the pJ/op barrier at a total power envelope of a few mW without compromising on programming productivity.

Biography: Luca Benini is Full Professor at the University of Bologna and he is the chair of digital Circuits and systems at ETHZ. He has served as Chief Architect for the Platform2012/STHORM project in STmicroelectronics, Grenoble in the period 2009-2013. He has held visiting and consulting researcher positions at EPFL, IMEC, Hewlett-Packard Laboratories, Stanford University. Dr. Benini’s research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. In these areas he has coordinated tens of funded projects, including an on-going ERC Advanced Grant on Multi-scale thermal management of Computing Systems. He has published more than 700 papers in peer-reviewed international journals and conferences, four books and several book chapters. He is a Fellow of the IEEE and a member of the Academia Europaea and has served for two terms as a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems.

Sedukhin Stanislav, University of Aizu, Japan 

Algorithms/Architecture Co-design for Exa-scale Computer 
To keep further historically exponential improvement of computer performance we have to overcome at least two fundamental barriers imposed by speed of light (frequency wall) and, related to it, heat generation (power wall).  In this talk, I will refresh the 50 years old and forgotten today idea of increasing the performance of a single-clock massively-parallel computer system by decreasing its operating frequency. This controversial idea is based on the fact that linear decreasing of frequency leads to the nonlinear enlargement of the system size, which can be used for increasing the concurrency level in a planar or cubical system. Moreover, decreasing the operating frequency results in a reduction of power consumption. I also will introduce a revised, computing-in-place version of the well-known systolic model of massively-parallel computing, where all initial/intermediate data are immediately available for concurrent computing and cyclical data exchange (reusing). In these array processors, the concurrency level might be scaled up to the maximum possible (extreme) number, which is equal to the size of computed-in-place matrix/tensor data. Co-design methodology of such extremely scalable algorithms and array processors will be illustrated on an example of multidimensional linear transforms, which are frequently the principal limiters that prevent many practical applications from scaling to the extremely large number of processing elements.

Biography: Stanislav G. Sedukhin received his Ph.D. in Computer Science from the Institute of Mathematics of the Siberian Branch (SB) of the USSR Academy of Sciences in 1981. In 1992 he received a second academic degree of Doctor of Physical and Mathematical Sciences (Habilitation) from the USSR (Russian) Academy of Sciences. He worked at the Institute of Mathematics and then at the Computing Center until 1993. From 1993 he is a Professor at the University of Aizu. From 2010 he served as Vice-President and Dean of the Graduate School. His interests in High-Performance Computing (HPC), parallel and distributed numerical computing, co-design of the extremely scalable VLSI-oriented algorithms/processors, clusters of computers and distributed OS for critical-mission applications. His recent research includes the architectural design of technology scalable cellular array processors to support scientific, engineering, and multimedia applications. He has published more than 170 articles, papers, chapters in books, reports and he is coauthor of several books. He is a member of the ACM, the IEEE Computer Society, and IEICE.

Hoi-Jun Yoo,  Korea Advanced Institute of Science and Technology (KAIST), South Korea

Humanistic Intelligence System: Bio-Inspired Multi-core Pattern Recognition Processor with on-chip Machine Learning
Multi-core processors are useful for the real-time pattern recognition for car navigation, autonomous robot, surveillance camera, and humanistic interface to consumer products. In this lecture, the benefits and methods of the integration of the neuro-fuzzy logic or soft-computing with multi-core processor will be explained, especially for high speed low power pattern recognition application. Analog-digital mixed mode neuro-fuzzy logic circuits are integrated with multi-cores to provide the ‘attention’ of the cluttered view to speed up the recognition process and improve its accuracy. In addition, learning in the neuro-fuzzy logic enables to adapt its operation to the input over time. The various multi-core architectures are implemented with the help of high performance Network on Chip, and the low power schemes such as DVFS and gate control. System demonstrations such as autonomous robot, car navigation, and HMD (K-Glass) will be introduced.

Biography: Prof. Hoi-Jun Yoo is the full professor of Department of Electrical Engineering at KAIST and the director of SDIA(System Design Innovation and Application Research Center). From 2003 to 2005, he was the full time Advisor to the Minister of Korean Ministry of Information and Communication for SoC and Next Generation Computing. His current research interests are Bio Inspired Intelligence SoC Design, Wearable Computing and Wearable Healthcare. He published more than 200 papers, and wrote 5 books including “Biomedical CMOS ICs”(2011, Springer). Dr. Yoo received the National Medal for his contribution to Korean Memory Industry in December of 2011, the Korean Scientist of the Month award in Dec. 2010, Best Research of KAIST Award in 2007, Design Award of 2001 ASP-DAC, and Outstanding Design Awards 2005, 2006, 2007 A-SSCC. He is an IEEE Fellow, a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC. He was the TPC Co-Chair of ISWC 2010, IEEE Distinguished Lecturer(’10-’11), and Asia Chair of ISSCC(‘10-‘11) and Vice TPC Chair of ISSCC 2014. He is TPC Chair of ISSCC 2015 and recognized as the top 4 paper-contributor for 2004-2013 ISSCCs and top 10 paper contributor for 1954-2013 ISSCCs

Jiang Xu, Hong Kong University of Science and Technology, Hong Kong SAR

Inter/Intra-Chip Optical Networks: Opportunities and Challenges
The performance and energy efficiency of a multi-core system is determined by not only its processor cores but also how efficiently they collaborate with each other. As new applications continuously require more communication bandwidth, metallic interconnects gradually become the bottlenecks of multi-core systems due to their high power consumption, limited bandwidth, and signal integrity issues. Optical interconnects are promising candidates to bring low power, high bandwidth, and low latency to address inter-chip as well as intra-chip communication challenges. Silicon-based photonic devices, such as optical waveguides and microresonators, have been demonstrated in CMOS-compatible fabrication processes and can be used to build inter/intra-chip optical networks. This talk will discuss the opportunities and challenges of this emerging technology and present our recent findings.

Biography: Jiang Xu received his Ph.D. degree from Princeton University. From 2001 to 2002, he worked at Bell Labs, NJ, as a Research Associate and discovered the First Generation Dilemma in platform-based SoC design methodologies. He was a Research Associate at NEC Laboratories America, NJ, from 2003 to 2005 and working on Network-on-Chip designs and implementations. He joined a startup company, Sandbridge Technologies, NY, from 2005 to 2007 and worked on the development and implementation of two generations of NoC-based ultra-low power Multiprocessor Systems-on-Chip for mobile platforms. Dr. Xu established Mobile Computing System Lab and Xilinx-HKUST Joint Lab at the Hong Kong University of Science and Technology. He currently serves as the Area Editor of NoC, SoC, and GPU for ACM Transactions on Embedded Computing Systems and Associate Editor for IEEE Transactions on Very Large Scale Integration (VLSI) Systems. He served on the steering committees, organizing committees, and technical program committees of many international conferences, including ICCAD, CASES, ISVLSI, ICCD, VLSI, EMSOFT, CODES+ISSS, VLSI-SoC, ICESS, RTCSA, NOCS, ASP-DAC, etc. Dr. Xu is an ACM Distinguished Speaker and a Distinguished Visitor of IEEE Computer Society. He authored or coauthored more than 70 book chapters and papers in peer-reviewed journals and international conferences. He and his students received Best Paper Award from IEEE Computer Society Annual Symposium on VLSI in 2009, and Best Poster Award from AMD Technical Forum and Exhibition in 2010. He coauthored a book titled Algorithms, Architecture and System-on-Chip Design for Wireless Applications (Cambridge University Press). His research areas include network-on-chip, multiprocessor system-on-chip, embedded system, computer architecture, low-power VLSI design, and HW/SW codesign.

Adel Alimi, University of Sfax, Tunisia

Big Data Streams Analytics – Analysis, Application and Challenges
Big data is not just about storage of and access to data. Analytics play a big role in making sense of that data and exploiting its value. Big Data analytics is considered an imperative aspect to be further improved in order to increase the operating margin of both public and private enterprises, and represents the next frontier for their innovation, competition, and productivity. Big Data are typically produced in different sectors of the above organizations, often geographically distributed throughout the world, and are characterized by a large size and variety. Therefore, there is a strong need for such Big Data streams analytics which is becoming a significant challenge and requires development of new types of algorithms. Most nowadays algorithms can’t easily scale up to big data. Plus there are challenges of high-dimensionality, velocity and variety. Thus the aim of this talk is to promote new advances and research directions in efficient and innovative algorithmic approaches to analyzing big data streams, implementations on different computing platforms (e.g. neuromorphic, GPUs, clouds, clusters) and applications of Big Data Analytics to solve real-world problems (e.g. weather prediction, transportation, energy management).

Biography: Adel M. Alimi (S’91, M’96, SM’00). He graduated in Electrical Engineering in 1990. He obtained a PhD and then an HDR both in Electrical & Computer Engineering in 1995 and 2000 respectively. He is full Professor in Electrical Engineering at the University of Sfax since 2006. Prof. Alimi is founder and director of the REGIM-Lab. on intelligent Machines. He published more than 300 papers in international indexed journals and conferences, and 20 chapters in edited scientific books. His research interests include applications of intelligent methods (neural networks, fuzzy logic, evolutionary algorithms) to pattern recognition, robotic systems, vision systems, and industrial processes. He focuses his research on intelligent pattern recognition, learning, analysis and intelligent control of large scale complex systems. He was the advisor of 24 Ph.D. thesis. He is the holder of 15 Tunisian patents. He managed funds for 16 international scientific projects. Prof. Alimi served as associate editor and member of the editorial board of many international scientific journals (e.g. “IEEE Trans. Fuzzy Systems”, “Pattern Recognition Letters”, “NeuroComputing”, “Neural Processing Letters”, “International Journal of Image and Graphics”, “Neural Computing and Applications”, “International Journal of Robotics and Automation”, “International Journal of Systems Science”, etc.). He was guest editor of several special issues of international journals (e.g. Fuzzy Sets & Systems, Soft Computing, Journal of Decision Systems, Integrated Computer Aided Engineering, Systems Analysis Modelling and Simulations). He organized many International Conferences ISI’12, NGNS’11, ROBOCOMP’11&10, LOGISTIQUA’11, ACIDCA-ICMI’05, SCS’04ACIDCA’2000. Prof. Alimi has been awarded with the IEEE Outstanding Branch Counselor Award for the IEEE ENIS Student Branch in 2011, with the Tunisian Presidency Award for Scientific Research and Technology in 2010, with the IEEE Certificate Appreciation for contributions as Chair of the Tunisia Computational Intelligence Society Chapter in 2010 and 2009, with the IEEE Certificate of Appreciation for contributions as Chair of the Tunisia Aerospace and Electronic Systems Society Chapter in 2009, with the IEEE Certificate of Appreciation for contributions as Chair of the Tunisia Systems, Man, and Cybernetics Society Chapter in 2009, with the IEEE Outstanding Award for the establishment project of the Tunisia Section in 2008, with the International Neural Network Society (INNS) Certificate of Recognition for contribution on Neural Networks in 2008, with the Tunisian National Order of Merit, at the title of the Education and Science Sector in 2006, with the IEEE Certificate of Appreciation and Recognition of contribution towards establishing IEEE Tunisia Section in 2001 and 2000. He is the Founder and Chair of many IEEE Chapters in Tunisia section. He is IEEE CIS ECTC Education TF Chair (since 2011), IEEE Sfax Subsection Chair (since 2011), IEEE Systems, Man, and Cybernetics Society Tunisia Chapter Chair (since 2011), IEEE Computer Society Tunisia Chapter Chair (since 2010), IEEE ENIS Student Branch Counselor (since 2010), He served also as Expert evaluator for the European Agency for Research. since 2009.

Xiang-Yang Li, Illinois Institute of Technology, USA

Large Scale Wireless Network Systems: Theory, Experience, and Lessons
Wireless sensor networks have been extensively studied from many aspects in the last decade. In this talk, I will share our experiences and lessons in building real operational large scale wireless sensor networking systems, our recent theoretical results on the asymptotical behavior of large scale sensor networks, and systems for coexisting ZigBee and WiFi networks. In the first part of the presentation, I will discuss the challenges and the lessons we learned from large scale operational sensor system deployments. In the second part of the presentation, I will summarize our results on the asymptotical network capacity of large scale wireless sensor networks (mainly the asymptotical multicast capacity in large scale wireless networks under various wireless interference models using various techniques such as optimal routing and scheduling, VC dimension, Percolation Theory), and the system implementation of ZIMO for harmonious coexistence of ZigBee and WiFi based on MIMO. Since 2007, collaborated with several schools, we deployed prototype sensor networks in the Yellow Sea (OceanSense 2007-2009), in Tian-Mu Mountain (GreenOrbs 2009-2011), and now we are working towards a 4000 sensor system (CitySee 2011-now) for urban sensing in WuXi City, China. Currently more than 1500 sensor nodes have been deployed in WuXi, which covers several square kilometers area. These systems provide us a unique opportunity to observe and understand the behavior of large scale sensor networking systems. Both our theoretical exercises and system investigations are motivated by and then validated in these real operational systems.

Biography:  Dr. Xiang-Yang Li is a professor at Computer Science Department of IIT, and EMC Visiting Chair Professor at Department of Computer Science and Technology, Tsinghua University (2014-2017). He was an Associate Professor (from 2006 to 2012) and Assistant Professor (from 2000 to 2006) of Computer Science at the Illinois Institute of Technology. He is recipient of China NSF Outstanding Overseas Young Researcher (B). Dr. Li received MS (2000) and PhD (2001) degree at Department of Computer Science from University of Illinois at Urbana-Champaign. He received a Bachelor degree at Department of Computer Science and a Bachelor degree at Department of Business Management from Tsinghua University, P.R. China, both in 1995. He published a monograph “Wireless Ad Hoc and Sensor Networks: Theory and Applications”. He also co-edited the book “Encyclopedia of Algorithms”. The research of Dr. Li has been supported by NSF of USA, RGC of HongKong, and NSF of China. His research interests include cyber physical systems, wireless networks, mobile computing, privacy and security, and algorithms. Dr. Li is an editor of several journals, including IEEE Transaction on Parallel and Distributed Systems, IEEE Transaction on Mobile Computing. He served at various capacities (conference chair, TPC chair, or local arrangement chair) in a number of conferences. He has graduated eleven PhD students since 2004, and co-advised 15 PhD students since 2005.

Minyi GuoShanghai Jiao Tong University (SJTU), China

Energy Efficient Data Access and Storage in Multi- and Many-core Systems
The processor has dominated energy consumption in the server in the past. However, as processors have become more energy efficient, their contribution has been decreasing. On the contrary, energy consumed by data access and storage is growing, since multi- and many-core severs are requiring increased main memory bandwidth/capacity, large register file and extra-large scale storage system. Accordingly, energy consumed by data access and storage is approaching or even surpassing that consumed by processors in many servers.
In this talk, we will present our continuing efforts to improve the energy efficiency of data access and storage. We propose a series of approaches with hardware-software cooperation to save energy consumption of L1 Cache, main memory, storage system and register file of GPGPU. Software and hardware co-design provides both flexibility and efficiency for reducing data access and storage energy.

Biography: Minyi Guo received the PhD degree in computer science from the University of Tsukuba, Japan. He is currently Zhiyuan chair professor and head of the Department of Computer Science and Engineering, Shanghai Jiao Tong University (SJTU), China. He received the national science fund for distinguished young scholars from NSFC in 2007. His research interests include parallel and distributed computing, compiler optimizations, embedded systems, pervasive computing, and bioinformatics. He has more than 300 publications in major journals and international conferences in these areas. Dr. Guo is on the editorial board of the journals IEEE Transactions on Parallel and Distributed Systems and IEEE Transactions on Computers. He is a senior member of the IEEE, member of ACM, IEICE IPSJ, and CCF.