Seung Jong Choi, Senior VP(System IC Center, LG Electronics Inc.)

TV SoC Solutions for the Immersive Display and Intelligent Platform (10:00 AM, September 18, 2017)

Abstract: Since analog to digital transition, TV industry has been changing very rapidly to launch 3DTV, Smart TV, UHD TV, and OLED TV to the market. On the one hand, this technology trend results from the fast TV panel innovation including PDP/LCD/OLED. On the other hand, the concept of the intelligent TV appears reflecting demand for the smart user experiences along with the evolution of the smart phone. This keynote starts with the importance of TV display, emphasizing the characteristics of the human visual system. Major advantages of newly emerging OLED panel technology are explained over the conventional LCD. Forecasting the future of TV, two main keywords are given, that is, the immersive viewing experiences and the intelligent platform. TV SoC plays a crucial role for TV platforms. LG has been developing TV SoCs as a market-leading system company to differentiate system with its own SoC solutions. This talk introduces LG TV SoC R&D activities, and achievements.

Biography: Dr. Seung-Jong Choi was born in Seoul, Korea, in 1964. He received the B.S. degree from Seoul National University, Seoul, Korea, in 1987, the M.S. degree from Korea Advanced Institute of Science and Technology, Taejon, Korea, in 1989, and Ph.D. degree from Rensselaer Polytechnic Institute, Troy, NY, in 1996, all in electrical engineering. His doctoral research was on video compression and video signal processing. Since 1989, he has been at LG Electronics Inc. and is presently a Senior Vice President and the Director of the System IC Center, Seoul, Korea. His main research activities have been related with TV and Digital TV SoCs. He has been developing multiple generations of DTV SoC solutions, and successfully applied them to the LG DTV product lineups, so far. Currently, he is leading the R&D activities on SoC solutions for the OLED TV, mobile and automotive products.

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Jae Choel Son, Senior VP(SoC IP Development Team, Samsung Electronics Co., Ltd.)

High-performance Mobile MP-SoC Design: Walls and Breakthroughs (10:00 AM, September 19, 2017)

Abstract: Multiple aspects that have enabled continuous innovations so far in mobile SOC design start to face walls. First, the process shrink is getting slower. Although the transistor size gets smaller, the density does not scale as before due to the fact that metal wire consumes more spaces. Transistor speed is not getting faster either, and wire delay, which becomes a dominant factor in speed path, is limiting the clock frequency even more. As the supply voltage is not getting lower, the power efficiency improvement is also being diminished. Not only the semiconductor process technology but also traditional architectural efforts are hitting limits. Micro-architecture evolutions to increase instruction level parallelism like wide pipeline and aggressive out-of-order scheduling cannot make significant improvements any longer. Even though GPU could maximize the parallelism by improving the core micro-architecture and by adopting multi-core, it starts to struggle with the rapid increase of bandwidth requirement due to increase of screen resolution and performance requirement. Big data access for deep learning or volume rendering of medical images also requires huge data bandwidth which current memory architecture struggles to support. In wireless communication, conventional technologies to maximize bandwidth by improving channel coding, modulation, and beam forming within frequency bandwidth of several hundreds of MHz to several GHz are also reaching limitations. In order to overcome these limitations, industry should put effort to find breakthroughs in new directions from the perspectives of process technology, physical implementation, SoC architecture, thermal design, and total system design optimization, which will be discussed in this presentation.

Biography: Dr. Jae Cheol Son is currently Senior Vice President at SoC IP Development Team of Samsung Electronics, where he leads the high-performance low-power IP development including CPU, GPU and modem. Prior to joining Samsung Electronics, he held various management and engineer positions at Sun Microsystems and Luminous Networks, where he focused on development of high-performance microprocessors and advanced ASIC products. He received B.S. degree from Yonsei University, Seoul, Korea, and M.S. and Ph.D. degrees from KAIST, Daejeon, Korea, all in electrical engineering. His research interests include high-performance microprocessor design, multimedia processing, and statistical signal processing. He is a senior member of IEEE.


Hideharu Amano, Keio University, Japan

A building block computing system for AI applications (3:30 PM, September 19, 2017)

Abstract: Recent remarkably developing application around IoT, robotics, and automatic mobile control requires systems with various functions with limited power consumption.  Developing System-on-Chip (SoC)s for each target application has become difficult because of growing non-recurring engineering cost of recently advanced process technology. Instead, we have been developing a building block computing system which can build various target systems just by stacking small chips by using a wireless inductive coupling through-chip interface. Here, its second prototype called Cube-2 is introduced. Four chips: Geyser-SCM, a low power MIPS-compatible CPU, CC-SOTB2, a coarse-grained reconfigurable accelerator for image processing,  SNACC, a convolutional neural network accelerator, and KVS, an accelerator for key value store database systems, can be stacked to form an AI system.  By changing the type and number of building block chips, a system can be tailored to the target application.

Biography: Hideharu Amano is a professor, department of information and computer science, Keio University. His research interest includes parallel computer architecture, reconfigurable systems and interconnection network.

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