Power-Aware Testing for Low-Power VLSI Circuits
Xiaoqing Wen, Kyushu Institute of Technology, Japan
Abstract: Low-power VLSI circuits are indispensable for all types of modern electronic devices, from battery-driven mobile gadgets to harvested-energy-driven IoT systems. However, the testing of such low-power VLSI circuits has become a big challenge, especially due to the excessive power dissipation during scan testing. This paper will highlight three major test-power-induced problems (namely heat, false timing failures, clock stretch) and describe how to mitigate them with power-aware VLSI testing. Future research directions in this field will also be discussed.
Biography: Xiaoqing WEN received the B.E. degree from Tsinghua University, China, in 1986, the M.E. degree from Hiroshima University, Japan, in 1990, and the Ph.D. degree from Osaka University, Japan, in 1993. He was an Assistant Professor with Akita University, Japan, from1993 to 1997, and a Visiting Researcher with the University of Wisconsin–Madison, USA, from Oct. 1995 to Mar. 1996. He joined SynTest Technologies Inc., USA, in 1998, and served as its Vice President and Chief Technology Officer until 2003. He joined Kyushu Institute of Technology, Japan, in 2003, where he is currently a Professor of the Department of Computer Science and Networks. He founded Dependable Integrated Systems Research Center at Kyushu Institute of Technology in 2013 and served as its Director until 2015. He is a Co-Founder and Co-Chair of the Technical Activity Committee on Power-Aware Testing under Test Technology Technical Council (TTTC) of IEEE Computer Society. He is an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (TVLSI) and Journal of Electronic Testing: Theory and Applications (JETTA). He co-authored and co-edited the latest VLSI test textbook (VLSI Test Principles and Architectures: Design for Testability) in 2006 and the first comprehensive book on power-aware VLSI testing (Power-Aware Testing and Test Strategies for Low Power Devices) in 2009. His research interests include design, test, and diagnosis of VLSI circuits. He has published more than 200 peer-reviewed papers and has conducted 19 tutorials on low-power VLSI testing. He holds 43 U.S. Patents and 14 Japan Patents. He received the 2008 Society Best Paper Award from the Information Systems Society (ISS) of the Institute of Electronics, Information and Communication Engineers (IEICE). He is a Fellow of IEEE, a Senior Member of Information Processing Society of Japan (IPSJ), and a Senior Member of IEICE. (http://aries3a.cse.kyutech.ac.jp/~wen)
Machine Learning based Physical Hardware Attacks: A Security Threat to Encrypted Chips and Multicore SoCs
Bah-Hwee Gwee, Nanyang Technological University, Singapore
Abstract:Mobile devices, Autonomous vehicles, UAVs, IoT devices and many other embedded systems often demand complex security features, including cryptography, tamper resistance, stealth, and etc., by means of hardware approaches and/or software approaches to prevent data leakages to unauthorized intruders. The physical hardware attacks or commonly known as side channel attacks have been employed to extract the secret keys of the encrypted algorithms implemented in hardware devices by analyzing their physical parameters such as power dissipation, electromagnetic interference and timing information.
In this presentation, we will discuss physical hardware security from both circuit and chip levels, and present how conventional and machine learning techniques can be utilized for the attacks and countermeasures. At the circuit level, we will first provide an overview of the different cryptography algorithms and present the side channel attacks, particularly the powerful Correlation Power Analysis (CPA) and Correlation Electromagnetic Analysis (CEMA) with a leakage model that can be used to reveal the secret keys of the cryptosystems. We will then discuss several countermeasure techniques including vertical and horizontal hidings and present how highly secured microchips including multi-core and pipeline processors can be designed based on these techniques. We then present the profiling and non-profiling machine learning techniques which can be effectively employed in the side channel attacks.
Biography :Dr Bah-Hwee Gwee received his B.Eng degree from University of Aberdeen, UK, in 1990. He received his MEng and PhD degrees from Nanyang Technological University in 1992 and 1998 respectively. He was an Assistant Professor of School of EEE, NTU from 1999 to 2005. He is currently an Associate Professor in School of EEE, NTU. He has worked on a number of research projects with research grant amounting to S$8m (~US$5.7m). He was the principal investigator of the research projects from MoE Academic Research Tier-2 grant of S$1.3m (~US$860k), ASEAN-EU University Network Programme grant of €200k and the Defense Science Organization grant of S$3.25m (~US$2.32m). He was also the Co-Principal Investigator of NTU-Panasonic research collaboration amounting to S$1m (~US$800k) and DARPA project of ~US$350k, Linkoping University – NTU joint research collaboration of S$660k (~US$400k), The Agency for Science, Technology and Research (A*STAR) – PSF research project of S$700k ((USD500k). His research interests include low power asynchronous IC design, Class-D amplifiers, digital signal processing and soft computing. He has published more than 140 technical papers, 6 patents (3 granted in USA) and started 2 Start-up Companies in 2005 and 2020.
He was the Chairman of IEEE-Singapore Circuits and Systems Chapter in 2005, 2006, 2013 and 2016. He is the Chairman of IEEE Circuits and Systems Society – DSPTC (2018-2020). He was the General Co-Chair of IEEE DSP 2018 and IEEE SOCC 2019. He was the organizing committee of the IEEE Bio-CAS 2004, IEEE APCCAS 2006 and the TPC Chair of International Symposium on Integrated Circuits (ISIC 2007, ISIC 2011 and ISIC 2016). He has also served as Associate Editors of a number of journals, including IEEE Transactions of Circuits and Systems II – Brief Express (2010-2011, 2018-2019 and 2020-2021), IEEE Transactions of Circuits and Systems I – Regular Papers (2012-2013) and Journal of Circuits, Systems and Signal Processing (2007-2012). He was awarded Temasek Laboratories @ NTU Best Publication Award in 2012 and the Teaching Excellence Award (Year 3) in 2013. He was an IEEE Distinguished Lecture for Circuits and Systems Society in 2009-2010 and in 2017-2018. He was awarded the Singapore Defence Technology Prize in 2016.
Models of computation for energy-efficient time-aware distributed embedded systems
Jeronimo Castrillon, TU Dresden, Germany
Abstract: Programming heterogeneous and distributed manycores under timing constraints in cyber-physical systems is an extremely hard task. Managing reactive behaviour to outside stimuli, adapting to variable workloads and handling parallelism while ensuring correct and time-predictable execution are examples of key challenges in these kinds of systems. This talk discusses the role of formal models of computation to help architect programming methodologies, making it easier to manage the complexity and provide guarantees than with ad-hoc programming models. We will discuss dataflow-based programming for joint optimization of multiple adaptable applications while respecting real-time constraints. We will then introduce the reactor model which adds time semantics to dataflow to support time-determinism when needed and to account for reactive behavior. The benefits and overheads of this model-based approach to programming distributed embedded systems will be analysed with use cases from the automotive and 5G-communication domains.
Biography: Jeronimo Castrillon is a professor in the Department of Computer Science at the TU Dresden, where he is also affiliated with the Center for Advancing Electronics Dresden (CfAED). He received the Electronics Engineering degree from the Pontificia Bolivariana University in Colombia in 2004, the master degree from the ALaRI Institute in Switzerland in 2006 and the Ph.D. degree (Dr.-Ing.) with honors from the RWTH Aachen University in Germany in 2013. His research interests lie on methodologies, languages, tools and algorithms for programming complex computing systems. He has more than 100 international publications and has been a member of technical program and organization committees in international conferences and workshops (e.g., DAC, DATE, ESWEEK, CGO, LCTES, Computing Frontiers, ICCS and FPL). He is also a regular reviewer for ACM and IEEE journals (e.g., IEEE TCAD, IEEE TPDS, ACM TODAES and ACM TECS). In 2014 Prof. Castrillon co-founded Silexica GmbH/Inc, a company that provides programming tools for embedded multicore architectures. Prof. Castrillon is Senior Member IEEE, Member ACM and was a founding member (2017-2019) of the executive committee of the ACM “Future of Computing Academy” (FCA).
***Two to three other outstanding KN speakers from Academia and Industry will be added here soon.