{"id":11148,"date":"2026-02-01T04:13:50","date_gmt":"2026-02-01T04:13:50","guid":{"rendered":"https:\/\/mcsoc-forum.org\/site\/?page_id=11148"},"modified":"2026-09-29T02:24:36","modified_gmt":"2026-09-29T02:24:36","slug":"neurocore","status":"publish","type":"page","link":"https:\/\/mcsoc-forum.org\/2027\/index.php\/neurocore\/","title":{"rendered":"2027 MCSoC-NeuroCore Global Summit"},"content":{"rendered":"\n<figure class=\"wp-block-image size-full is-resized\"><img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/08\/mcsoc-neurocore-banner.png\" alt=\"\" style=\"width:100%;height:auto\"\/><\/figure>\n\n\n\n<p class=\"wp-block-paragraph\">The <strong>2027 MCSoC\u2013NeuroCore Global Summit<\/strong> is organized within the <strong>IEEE MCSoC Forum<\/strong> program and serves as a dedicated venue for advancing <strong>Neuromorphic Systems<\/strong> and <strong>Brain\u2011Inspired Computing<\/strong>. NeuroCore brings together leading researchers and practitioners to explore the principles, architectures, and technologies that enable intelligent computation grounded in neural and cognitive models. Its mission is to establish a rigorous foundation for devices, circuits, architectures, algorithms, and large\u2011scale systems that emulate the efficiency, adaptability, and parallelism of biological intelligence. As neuromorphic engineering expands across edge intelligence, autonomous systems, and emerging AI paradigms, NeuroCore provides a focused forum for breakthroughs that bridge neuroscience, computing, and next\u2011generation cognitive architectures\u2014enabling scalable, energy\u2011efficient, and robust intelligent systems for real\u2011world deployment.<\/p>\n\n\n\n<h3 class=\"wp-block-heading\">Program Chairs<\/h3>\n\n\n\n<style>\n  .nc-chair-row {\n    display: flex;\n    flex-wrap: wrap;\n    justify-content: center;\n    gap: 24px;\n    margin: 20px 0 30px;\n  }\n  .nc-chair-member {\n    text-align: center;\n    width: calc(33.333% - 24px);\n    min-width: 170px;\n  }\n  .nc-chair-member img {\n    width: 160px;\n    height: 160px;\n    object-fit: cover;\n    border-radius: 50%;\n    border: 3px solid #0073AA;\n    margin: 0 auto 10px;\n    display: block;\n  }\n  .nc-chair-name {\n    font-weight: bold;\n    color: #333;\n    font-size: 16px;\n    margin-top: 5px;\n  }\n  .nc-chair-affil {\n    font-size: 14px;\n    color: #555;\n    line-height: 1.3;\n  }\n  @media (max-width: 600px) {\n    .nc-chair-member { width: 100%; }\n  }\n<\/style>\n\n<div class=\"nc-chair-row\">\n  <div class=\"nc-chair-member\">\n    <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2026\/02\/amir-2025-no-bg.jpg\" alt=\"Amirreza Yousefzadeh\">\n    <p class=\"nc-chair-name\">Amirreza Yousefzadeh<\/p>\n    <p class=\"nc-chair-affil\">University of Twente, The Netherlands<\/p>\n  <\/div>\n  <div class=\"nc-chair-member\">\n    <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/09\/xabi_iturbe.png\" alt=\"Xabier Iturbe\">\n    <p class=\"nc-chair-name\">Xabier Iturbe<\/p>\n    <p class=\"nc-chair-affil\">IK4-Ikerlan Research Alliance, Spain<\/p>\n  <\/div>\n  <div class=\"nc-chair-member\">\n    <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2026\/02\/Dr.-AlbertoMarchisio.jpg\" alt=\"Alberto Marchisio\">\n    <p class=\"nc-chair-name\">Alberto Marchisio<\/p>\n    <p class=\"nc-chair-affil\">New York University (NYU) Abu Dhabi, UAE<\/p>\n  <\/div>\n<\/div>\n\n\n\n<h3 class=\"wp-block-heading\"><strong>Topics of Interest<\/strong><\/h3>\n\n\n\n<ul class=\"wp-block-list\">\n\n<li><strong>Track1: Brain\u2011Inspired and Neuromorphic System Architectures<\/strong><br>\n<em>Track Chair: Amirreza Yousefzadeh, University of Twente, The Netherlands<\/em>\n  <ul>\n    <li>Brain-inspired computational primitives and network topologies.<\/li>\n    <li>System-level architectures combining neuromorphic and conventional cores.<\/li>\n    <li>Scalability and interconnect strategies for large neuromorphic systems.<\/li>\n    <li>Hierarchical and modular organization of neuromorphic architectures.<\/li>\n    <li>Cross-layer design linking neural models to system architecture.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track2: In\u2011Memory and Event\u2011Driven Computing Architectures<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Processing-in-memory and near-memory computing for neuromorphic workloads.<\/li>\n    <li>Event-driven and asynchronous dataflow architectures.<\/li>\n    <li>Memory technologies enabling in-situ computation.<\/li>\n    <li>Sparse and event-triggered data movement strategies.<\/li>\n    <li>Trade-offs between in-memory compute density and throughput.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track3: Architectures for Large\u2011Scale Spiking Neural Systems<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Scalable spiking neural network (SNN) hardware architectures.<\/li>\n    <li>Routing and communication fabrics for large-scale SNNs.<\/li>\n    <li>Hardware support for spike-based learning rules.<\/li>\n    <li>Synchronization and timing strategies across large spiking arrays.<\/li>\n    <li>Fault tolerance and reliability in large-scale SNN deployments.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track4: Neuromorphic Intelligence: Circuits, Systems, and Architectures<\/strong><br>\n<em>Track Chair: Kaijie Wei, Keio University, Japan<\/em>\n  <ul>\n    <li>Circuit-level innovations for neuromorphic intelligence.<\/li>\n    <li>Cross-layer system design from devices to architectures.<\/li>\n    <li>Integration of sensing, memory, and computation.<\/li>\n    <li>Analog and digital circuit co-design for neuromorphic intelligence.<\/li>\n    <li>System-level trade-offs between accuracy, latency, and power.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track5: Analog, Mixed\u2011Signal, and Memristive Neuromorphic Systems<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Analog and mixed-signal circuits for neuromorphic computation.<\/li>\n    <li>Memristive device integration for synaptic emulation.<\/li>\n    <li>Noise tolerance and variability mitigation in analog neuromorphic systems.<\/li>\n    <li>Calibration and compensation techniques for analog drift.<\/li>\n    <li>Hybrid analog-digital neuromorphic circuit design.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track6: Neuromorphic Approaches for Foundation Models and On\u2011Device AI<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Neuromorphic acceleration for foundation model inference.<\/li>\n    <li>Efficient on-device deployment of large models via spiking or event-driven methods.<\/li>\n    <li>Hybrid neuromorphic\/conventional pipelines for edge AI.<\/li>\n    <li>Model compression and sparsification for neuromorphic deployment.<\/li>\n    <li>Latency and energy trade-offs for on-device foundation model inference.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track7: Simulation, Benchmarking, and Evaluation of Neuromorphic Systems<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Simulation frameworks and toolchains for neuromorphic hardware.<\/li>\n    <li>Benchmarking methodologies and standardized workloads.<\/li>\n    <li>Reproducibility and evaluation metrics for neuromorphic performance.<\/li>\n    <li>Cross-platform comparison of neuromorphic simulators and emulators.<\/li>\n    <li>Open datasets and benchmark suites for neuromorphic research.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track8: Energy\u2011Efficient Neuromorphic Accelerators for Edge and Cloud<\/strong><br>\n<em>Track Chair: Farooq Khanday, University of Kashmir, India<\/em>\n  <ul>\n    <li>Low-power neuromorphic accelerator design.<\/li>\n    <li>Energy-efficiency trade-offs across edge and cloud deployment.<\/li>\n    <li>Power management techniques for neuromorphic hardware.<\/li>\n    <li>Dynamic voltage and frequency scaling for neuromorphic accelerators.<\/li>\n    <li>Thermal and power budget constraints in deployment scenarios.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track9: Brain\u2011Inspired Algorithm\u2013Hardware Co\u2011Optimization<\/strong><br>\n<em>Track Chair: Alberto Marchisio, New York University Abu Dhabi, UAE<\/em>\n  <ul>\n    <li>Joint optimization of learning algorithms and hardware constraints.<\/li>\n    <li>Hardware-aware training methods for neuromorphic systems.<\/li>\n    <li>Co-design methodologies bridging algorithms and circuits.<\/li>\n    <li>Quantization and precision-reduction strategies for neuromorphic learning.<\/li>\n    <li>Automated design-space exploration for algorithm\u2013hardware pairs.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track10: Neuromorphic Approaches for Foundation Models and On\u2011Device AI<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Edge deployment strategies for foundation-model-derived workloads.<\/li>\n    <li>Neuromorphic techniques for continual and on-device learning.<\/li>\n    <li>Cross-domain applications combining neuromorphic and machine learning approaches.<\/li>\n    <li>Privacy-preserving on-device inference using neuromorphic methods.<\/li>\n    <li>Adaptation and personalization of models at the edge.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track11: Materials and Devices for Ultra\u2011Low\u2011Power Neuromorphic Systems<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Emerging materials for ultra-low-power synaptic and neuronal devices.<\/li>\n    <li>Device-level characterization and reliability studies.<\/li>\n    <li>Novel fabrication approaches for neuromorphic hardware.<\/li>\n    <li>Scaling limits and variability of emerging neuromorphic devices.<\/li>\n    <li>Integration pathways from device to system-level demonstration.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track12: Neuromorphic Software Stacks, Compilers, and Programming Models<\/strong><br>\n<em>Track Chair: TBC<\/em>\n  <ul>\n    <li>Compiler infrastructure for neuromorphic hardware targets.<\/li>\n    <li>Programming abstractions and frameworks for spiking systems.<\/li>\n    <li>Toolchains bridging high-level models and neuromorphic deployment.<\/li>\n    <li>Debugging, profiling, and visualization tools for neuromorphic software.<\/li>\n    <li>Interoperability standards across neuromorphic software stacks.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track13: Cognitive Computing Models and Brain\u2011Derived Algorithms<\/strong><br>\n<em>Track Chair: Sichen Tao, Tohoku University, Japan<\/em>\n  <ul>\n    <li>Computational models inspired by cognitive and neural processes.<\/li>\n    <li>Brain-derived algorithms for perception and decision-making.<\/li>\n    <li>Cognitive architectures for adaptive intelligent systems.<\/li>\n    <li>Models of attention, memory, and learning inspired by neuroscience.<\/li>\n    <li>Evaluation of cognitive models against biological plausibility.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track14: Brain\u2011Inspired Hardware for Cognitive and Adaptive Systems<\/strong><br>\n<em>Track Chair: Khanh Dang, The University of Aizu, Japan<\/em>\n  <ul>\n    <li>Hardware platforms supporting cognitive-level processing.<\/li>\n    <li>Adaptive and self-organizing neuromorphic hardware.<\/li>\n    <li>Integration of cognitive models into embedded hardware.<\/li>\n    <li>On-chip learning and plasticity mechanisms for adaptive systems.<\/li>\n    <li>Real-time cognitive processing under resource constraints.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track15: Novel Devices for Neuromorphic Computing: Memristors, PCM, RRAM<\/strong><br>\n<em>Track Chair: Xumeng Zhang, Fudan University, China<\/em>\n  <ul>\n    <li>Memristor, PCM, and RRAM device physics for neuromorphic applications.<\/li>\n    <li>Synaptic and neuronal emulation using emerging non-volatile devices.<\/li>\n    <li>Reliability, endurance, and scalability of novel neuromorphic devices.<\/li>\n    <li>Multi-level and analog switching behavior in emerging devices.<\/li>\n    <li>Array-level integration and yield considerations.<\/li>\n  <\/ul>\n<\/li>\n\n<li><strong>Track16: 3D Integrated and Heterogeneous Neuromorphic Systems<\/strong><br>\n<em>Track Chair: Xabier Iturbe, IK4-Ikerlan Research Alliance, Spain<\/em>\n  <ul>\n    <li>3D integration techniques for neuromorphic system stacking.<\/li>\n    <li>Heterogeneous integration of neuromorphic and conventional compute layers.<\/li>\n    <li>Thermal and interconnect challenges in 3D neuromorphic systems.<\/li>\n    <li>Chiplet-based approaches to heterogeneous neuromorphic integration.<\/li>\n    <li>Vertical interconnect and through-silicon-via strategies for 3D stacks.<\/li>\n  <\/ul>\n<\/li>\n\n<\/ul>\n\n\n\n<style>\n  .paper-submission-highlight {\n    background-color: #f6f7f9;\n    border-left: 6px solid #2c3e50;\n    padding: 35px;\n    margin: 25px 0;\n    border-radius: 4px;\n    font-family: -apple-system, BlinkMacSystemFont, \"Segoe UI\", Roboto, Oxygen-Sans, Ubuntu, Cantarell, \"Helvetica Neue\", sans-serif;\n    color: #333;\n    box-shadow: 0 3px 6px rgba(0,0,0,0.08);\n  }\n  .paper-submission-highlight h2 {\n    margin-top: 0;\n    color: #2c3e50;\n    font-size: 2rem;\n    font-weight: 700;\n    margin-bottom: 15px;\n  }\n  .paper-submission-highlight p {\n    font-size: 1.25rem;\n    line-height: 1.6;\n    margin-bottom: 25px;\n  }\n  .submission-btn {\n    display: inline-block;\n    background-color: #0073aa;\n    color: #ffffff !important;\n    padding: 15px 30px;\n    font-size: 1.15rem;\n    text-decoration: none;\n    border-radius: 5px;\n    font-weight: bold;\n    transition: background-color 0.3s ease;\n    text-align: center;\n  }\n  .submission-btn:hover {\n    background-color: #005177;\n    text-decoration: none;\n    cursor: pointer;\n  }\n<\/style>\n\n<div class=\"paper-submission-highlight\">\n  <h2>Paper Submission<\/h2>\n  <p>\n    All papers must be submitted electronically through EDAS. Authors are encouraged to review the detailed submission instructions before uploading their manuscripts.\n  <\/p>\n  <a href=\"https:\/\/mcsoc-forum.org\/2027\/index.php\/paper-submission\/\" class=\"submission-btn\" target=\"_blank\" rel=\"noopener noreferrer\">\n    View Submission Guidelines\n  <\/a>\n<\/div>\n\n\n\n<h2 style=\"color: #2E7D32; margin-top: 0; margin-bottom: 15px; border-bottom: 2px solid #2E7D32; padding-bottom: 5px;\">\n  Proceedings Publication and Indexing\n<\/h2>\n\n<div style=\"display: flex; flex-wrap: wrap; justify-content: space-around; align-items: center; margin: 20px 0; gap: 25px;\">\n  <div style=\"text-align: center;\">\n    <p style=\"font-size: 11px; font-weight: bold; color: #388E3C; margin-bottom: 5px; text-transform: uppercase;\">Indexed by<\/p>\n    <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/01\/Scopus_logo.svg_-1.png\" alt=\"Scopus Logo\" style=\"max-height: 40px; width: auto;\">\n  <\/div>\n  <div style=\"text-align: center;\">\n    <p style=\"font-size: 11px; font-weight: bold; color: #388E3C; margin-bottom: 5px; text-transform: uppercase;\">Published in<\/p>\n    <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2025\/03\/IEEE-Xplore.png\" alt=\"IEEE Xplore Logo\" style=\"max-height: 120px; width: auto;\">\n  <\/div>\n<\/div>\n\n<p style=\"font-size: 16px; line-height: 1.6; margin-bottom: 18px; text-align: justify;\">\n  The conference proceedings, including all technical tracks, special tracks, and special sessions and workshop papers, will be published by <strong>IEEE Conference Proceedings<\/strong>, which will be included in the <strong>Computer Society Digital Library (CSDL)<\/strong> and <strong>IEEE Xplore<\/strong>, subject to meeting IEEE Xplore&#8217;s scope and quality requirements.\n<\/p>\n\n<div style=\"font-size: 15px; line-height: 1.6; background-color: #E8F5E9; padding: 14px; border-left: 5px solid #2E7D32; border-radius: 4px; margin-bottom: 25px;\">\n  All CPS conference publications are also submitted for indexing to <strong>EI&#8217;s Engineering Information Index, Compendex, ISI Thomson&#8217;s Scientific and Technical Proceedings, Scopus, ISTP\/ISI Proceedings<\/strong>.\n<\/div>\n\n\n\n<hr class=\"wp-block-separator has-alpha-channel-opacity\"\/>\n\n\n\n<div style=\"font-family: Arial, sans-serif; text-align:center;\">\n  <h3 style=\"color:#2E7D32; border-bottom: 2px solid #2E7D32; padding-bottom: 6px; margin-bottom: 20px;\">\n    PATRON, HOST, and SPONSORS\n  <\/h3>\n  <div style=\"width:100%; overflow:hidden; position:relative; padding:10px 0;\">\n    <div style=\"display:flex; align-items:center; gap:40px; animation: slide-logos 25s linear infinite; white-space:nowrap;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2022\/01\/ASL-e1624758839307-3.jpg\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/08\/UEC-LOGO.jpg\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/01\/UoA-Logo.png\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/08\/giatec-logo-light.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/01\/logo-IEEE-CS-80th-FINAL_Black.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2022\/04\/IEEE-L.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2022\/06\/TCMM.jpg\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2022\/01\/ASL-e1624758839307-3.jpg\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/08\/UEC-LOGO.jpg\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/01\/UoA-Logo.png\" style=\"height:80px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/08\/giatec-logo-light.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2026\/01\/logo-IEEE-CS-80th-FINAL_Black.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/2027\/wp-content\/uploads\/2022\/04\/IEEE-L.png\" style=\"height:70px;\">\n      <img decoding=\"async\" src=\"https:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2022\/06\/TCMM.jpg\" style=\"height:70px;\">\n    <\/div>\n  <\/div>\n<\/div>\n<style>\n@keyframes slide-logos {\n  0%   { transform: translateX(0); }\n  100% { transform: translateX(-50%); }\n}\n<\/style>\n","protected":false},"excerpt":{"rendered":"<p>The 2027 MCSoC\u2013NeuroCore Global Summit is organized within the IEEE MCSoC Forum program and serves as a dedicated venue for advancing Neuromorphic Systems and Brain\u2011Inspired Computing. NeuroCore brings together leading researchers and practitioners to explore the principles, architectures, and technologies that enable intelligent computation grounded in neural and cognitive models. Its mission is to establish &hellip; <\/p>\n<p><a class=\"more-link btn\" href=\"https:\/\/mcsoc-forum.org\/2027\/index.php\/neurocore\/\">Continue reading<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-11148","page","type-page","status-publish","hentry","nodate","item-wrap"],"_links":{"self":[{"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/pages\/11148","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/comments?post=11148"}],"version-history":[{"count":120,"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/pages\/11148\/revisions"}],"predecessor-version":[{"id":12883,"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/pages\/11148\/revisions\/12883"}],"wp:attachment":[{"href":"https:\/\/mcsoc-forum.org\/2027\/index.php\/wp-json\/wp\/v2\/media?parent=11148"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}