Er Meng Joo, Nanyang Technological University, Singapore
Title: Artificial Intelligence:: Recent Developments and Futuristic Trends
Abstract: The quest for building human-like intelligence has gained enormous momentum in recent decades. Since the seminal works on Artificial Intelligence (AI), the desire of realizing the quest has become stronger. With the rapid developments in Science, Engineering and Technology, machines that mimic human intelligence have become a reality and sometimes indispensable parts in our daily life, such as Apple Siri and Google Voice. AI is the Science and Engineering that is concerned with the theory and practice of developing systems that exhibit the characteristics we associate with intelligence in human behavior: perception, natural language processing, reasoning, planning and problem solving, learning and adaptation, etc. In this talk, fundamentals and recent developments of AI techniques will be reviewed. The futuristic trends and challenges in AI will also be discussed.
Biography: Professor Er Meng Joo is currently a Full Professor in Electrical and Electronic Engineering, Nanyang Technological University, Singapore. He served as the Founding Director of Renaissance Engineering Programme and an elected member of the NTU Advisory Board and from 2009 to 2012. He served as a member of the NTU Senate Steering Committee from 2010 to 2012. He has authored five books entitled “Dynamic Fuzzy Neural Networks: Architectures, Algorithms and Applications” and “Engineering Mathematics with Real-World Applications” published by McGraw Hill in 2003 and 2005 respectively, and “Theory and Novel Applications of Machine Learning” published by In-Tech in 2009, “New Trends in Technology: Control, Management, Computational Intelligence and Network Systems” and “New Trends in Technology: Devices, Computer, Communication and Industrial Systems”, both published by SCIYO, 18 book chapters and more than 500 refereed journal and conference papers in his research areas of interest. Professor Er was bestowed the Web of Science Top 1 % Best Cited Paper and the Elsevier Top 20 Best Cited Paper Award in 2007 and 2008 respectively. In recognition of the significant and impactful contributions to Singapore’s development by his research projects, Professor Er won the Institution of Engineers, Singapore (IES) Prestigious Engineering Achievement Award twice (2011 and 2015). He is also the only dual winner in Singapore IES Prestigious Publication Award in Application (1996) and IES Prestigious Publication Award in Theory (2001). Recently, he was bestowed the Amity Researcher Award 2018 for his outstanding and significant contributions in Robotics and Automation. He received the Teacher of the Year Award for the School of EEE in 1999, School of EEE Year 2 Teaching Excellence Award in 2008, the Most Zealous Professor of the Year Award in 2009 and the Outstanding Mentor Award in 2014. He also received the Best Session Presentation Award at the World Congress on Computational Intelligence in 2006, Best Paper Award (First Prize) at the International Automatic Control Conference 2016, Best Presentation Award at the IEEE-sponsored International Conference on Intelligent Control, Power and Instrumentation (ICICPI) 2016 and Best Presentation Award at the IEEE-sponsored International Conference on Intelligent Autonomous System (ICoIAS) 2018 . On top of this, he has more than 70 awards received at international and local competitions. Currently, Professor Er serves as the Editor-in-Chief of 3 international journals, namely International Journal of Intelligent Autonomous Systems, Transactions on Machine Learning and Artificial Intelligence and the International Journal of Electrical and Electronic Engineering and Telecommunications. He also serves an Area Editor of International Journal of Intelligent Systems Science and an Associate Editor of 14 refereed international journals, namely IEEE Transaction on Cybernetics, Information Sciences, Neurocomputing, Asian Journal of Control, International Journal of Fuzzy Systems, ETRI Journal, International Journal of Humanoid Robots, International Journal of Modelling, Simulation and Scientific Computing, International Journal of Applied Computational Intelligence and Soft Computing, International Journal of Business Intelligence and Data Mining, International Journal of Fuzzy and Uncertain Systems, International Journal of Automation and Smart Technology, International Journal of Intelligent Information Processing and an editorial board member of the Open Automation and Control Systems Journal and the EE Times. Professor Er has been invited to deliver more than 60 keynote speeches and invited talks overseas. He has also been active in professional bodies. Under his leadership, the IEEE CIS Singapore Chapter won the CIS Outstanding Chapter Award in 2012 (The Singapore Chapter is the first chapter in Asia to win the award). He was bestowed the IEEE Outstanding Volunteer Award (Singapore Section) and the IES Silver Medal in 2011. He is listed in Who’s Who in Engineering, Singapore, Edition 2013.
Wei Zhang, Hong Kong University of Science and Technology, Hong Kong
Title: FPGA Based Acceleration for Big Data Processing: Challenges and Opportunities
With the rapidly rising demands of computing capability for big data processing, hardware accelerators are increasingly used in computing systems to satisfy the performance requirement. FPGAs are regarded as one of the promising hardware accelerators to implement various compute-intensive tasks due to their advantages of low power and massive parallelism. However, there are both challenges and opportunities faced by the community to employ FPGAs efficiently in such applications. In this talk, we will analyze the challenges and potential of using FPGAs for acceleration of big data processing applications including machine learning based processing in both the cloud and the edge devices. Particularly, although FPGAs can provide desirable
hardware solutions, it is not easy to implement and optimize FPGA based implementations, especially by designers who lack hardware background. We will present a series of design techniques and automation flows in high-level synthesis (HLS) to bridge this gap and facilitate the FPGA implementation with high performance and energy efficiency.
Biography: Wei Zhang is currently an Associate Professor with the Department of Electronic and Computer Engineering, the Hong Kong University of Science and Technology, Hong Kong, where she established the Reconfigurable System Laboratory. She was an Assistant Professor with the School of Computer Engineering, Nanyang Technological University, Singapore, from 2010 to 2013. She authored over 100 technical papers in referred international journals and conferences and authored three book chapters. Her current research interests include reconfigurable system, power and energy management, embedded system security, and emerging technology. Her team has won the best paper award in ISVLSI 2009 and ICCAD 2017. She currently serves as Associate Editor of the ACM Transactions on Embedded Computing Systems (TECS), Associate Editor of the IEEE Transaction on Very Large Scale Integration (TVLSI) Systems, Associate Editor of the IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), and Associate Editor of the ACM Journal on Emerging Technologies in Computing Systems (JETC). She also serves on many organization committees and technical program committees, such as DAC, ICCAD, ASPDAC, CASES, FPGA, FCCM, FPL, etc.
Massimo Alioto, National University of Singapore, Singapore
Title: Survival of the fittest: circuits and architectures with wide power-performance adaptation – Beyond voltage scaling and down to pWs
Wide power-performance adaptation is becoming crucial in always-on nearly real-time and energy-autonomous integrated systems that are subject to wide variability in the power availability and the performance target. Adaptation is indeed a prerequisite to assure continuous operation in spite of the widely fluctuating energy/power source (e.g., energy harvester), and to grant swift response upon the occurrence of events of interest (e.g., on-chip data analytics), while maintaining extremely low consumption in the common case. These requirements have led to the strong demand of a new breed of integrated systems having an extremely wide performance-power scalability and adaptation, beyond conventional voltage scaling or adaptive parallelism. In this context, systems being able to adapt to a wider performance-power range (“the fittest”) allow true continuous operation and adjustment to the power-performance profile required by the application (“survival”). In this talk, new techniques that drastically extend the performance-power scalability of digital circuits and architectures are presented. Silicon demonstrations of better-than-voltage-scaling adaptation to the workload are illustrated for both the data path (i.e., microarchitecture) and the clock path. Adaptation to a very wide range of energy/power availability is also discussed, presenting demonstrations of always-on systems (e.g., microcontrollers, power management units) with power down to sub-nW, and duty-cycled operation down to pW range. As an orthogonal design dimension, “just-enough” adaptation to the application-level quality requirement is shown to further extend the performance-power range by an order of magnitude or more. Under this energy-quality scaling framework, quality is treated as an explicit knob, eliminating the quality slack that is traditionally imposed by worst-case design across different applications (e.g., machine learning), contexts, datasets, and the pessimistic design margin to counteract process/voltage/temperature variations. Several silicon demonstrations are illustrated to quantify the benefits offered by wide power-performance adaptation, and identify opportunities and challenges for the decade ahead.
Biography: Massimo Alioto is with the ECE Department of the National University of Singapore, where he leads the Green IC group and the Integrated Circuits and Embedded Systems area. Previously, he held positions at the University of Siena, Intel Labs – CRL (2013), University of Michigan – Ann Arbor (2011-2012), University of California – Berkeley (2009-2011), EPFL – Lausanne. He is (co)author of 250+ publications on journals and conference proceedings, and three books with Springer. His primary research interests include ultra-low power circuits and systems, self-powered integrated systems, near-threshold circuits for green computing, widely energy-scalable integrated systems, circuits for machine intelligence, hardware security, and emerging technologies. He is the Editor in Chief of the IEEE Transactions on VLSI Systems, and was Deputy Editor in Chief of the IEEE Journal on Emerging and Selected Topics in Circuits and Systems. Prof. Alioto was the Chair of the “VLSI Systems and Applications” Technical Committee of the IEEE CASS (2010-2012), Distinguished Lecturer (2009-2010), and members of the Board of Governors (2015-2020). He served as Guest Editor of numerous journal special issues, Technical Program Chair of several IEEE conferences (ISCAS 2022, SOCC, PRIME, ICECS, VARI, NEWCAS, ICM), and TPC member (ISSCC, ASSCC). Prof. Alioto is an IEEE Fellow.
Jeronimo Castrillon, TU Dresden, Germany
Title: “Embedded manycore programming: From auto-parallelization to domain specific languages”
Abstract: Programming manycores remains a daunting task, especially in the presence of the heterogeneity and application constraints typical in the embedded domain.
This talk reviews efforts to cope with this complexity from the last 10+ years of research. It starts with the challenges faced by auto-parallelizing compilers, discussing how far they have made it since the start of the multi-core era. The talk also reviews explicit parallel programming and associated programming methodologies, with focus on recent advances that aim at increasing the adaptivity and robustness of dataflow applications. The talk then advocates for even higher-level programming abstractions in the form of domain specific languages, particularly important to deal with the increased complexity brought by emerging computing paradigms.
Biography: Jeronimo Castrillon is a professor in the Department of Computer Science at the TU Dresden. He received the Electronics Engineering degree from the Pontificia Bolivariana University in Colombia in 2004, the master degree from the ALaRI Institute in Switzerland in 2006 and the Ph.D. degree (Dr.-Ing.) with honors from the RWTH Aachen University in Germany in 2013. His research interests lie on methodologies, languages, tools and algorithms for programming complex computing systems. He has more than 60 international publications and has been a member of technical program and organization committees in international conferences and workshops (e.g., DAC, DATE, ESWEEK, CGO, LCTES, Computing Frontiers, ICCS and FPL). He is also a regular reviewer for ACM and IEEE journals (e.g., IEEE TCAD, IEEE TPDS, ACM TODAES and ACM TECS). In 2014 Prof. Castrillon co-founded Silexica GmbH, a company that provides programming tools for embedded multicore architectures. Since 2017, Prof. Castrillon is a member of the executive committee of the ACM “Future of Computing Academy”.
Hiroki Matsutani, Keio University, Japan
Title: “An On-Device Learning Approach for Unsupervised Anomaly Detection on Chip”
Abstract: Toward on-device learning for edge and IoT devices, we will introduce a neural-network based online sequential learning and unsupervised anomaly detection (OSL-UAD) approach and its hardware design. The target domain is originally production lines in factories, but our application is currently expanding, such as anomaly detections in datacenter, home, and UAVs. One of the biggest issues when applying AI to industries is to prepare accurate training data sets before deployment, because noise pattern (e.g., vibration) fluctuates and status of products/tools varies with time. The proposed on-device learning approach learns normal patterns including noises in a deployed environment extemporarily to detect unusual ones, so no prior training is needed. In this talk, we will introduce the algorithm and its related technologies, such as simplified computation method, stable learning method, forgetting method, and accuracy improvement method for multiple normal patterns, in addition to the hardware design for the on-chip learning for edge and IoT devices. We will also introduce some use cases.
Biography: Hiroki Matsutani received the BA, ME, and PhD degrees from Keio University, Yokohama, Japan, in 2004, 2006, and 2008, respectively. He is currently an associate professor in the Department of Information and Computer Science, Keio University. From 2009 to 2011, he was a research fellow (JSPS SPD) in the Graduate School of Information Science and Technology, The University of Tokyo, Tokyo, Japan. His research interests include the areas of computer architecture, accelerator, machine learning algorithm, and chip design. He served on TPC co-chair of NOCS 2016 and General co-chair of NOCS 2017. He also served on OC and/or TPC of related international conferences, such as DAC, DATE, ASP-DAC, ISLPED, CODES+ISSS, NOCS, and ICPP.