Preliminary Program

Last updated on October 10, 2021. 

This program is subject to change. Please confirm your name, affiliation, and paper’s title. If you find a mistake, please contact Prof. Khanh Dang (contact). The final version of the program will be released on December 1st, 2021. 

1. Program at a Glance 

2. Program Details

1-A: Multicore/Manycore SoC Applications 

Monday, December 20, 15:30 – 16:30 (Singapore time: GMT+8)
Session chair: Stéphane Louise (CEA, LIST, France) and William J. Song (Yonsei Univ, Korea) (TBC)
Room: Room-1, Zoom Link (TBC) 

  • 15:30   FPGA-based Implementation of the Stereo Matching Algorithm using High-Level Synthesis [slides.pdf], [recorded video]
    Iman Firmansyah (University of Tsukuba, Japan & Indonesian Institute of Sciences, Indonesia); Yoshiki Yamaguchi (University of Tsukuba, Japan) 
  • 15:50   Acceleration of Gravitation Field Analysis for Asteroids by GPU Computation [slides.pdf], [recorded video]
    Fumiya Kono, Naohito Nakasato and Naru Hirata (University of Aizu, Japan); Koji Matsumoto (National Astronomical Observatory of Japan (NAOJ), Japan) 
  • 16:10   Accelerated On-Chip Algorithm based on Semantic Region-based Partial Difference Detection for LiDAR-Vision Depth Data Transmission Reduction in Lightweight Controller Systems of Autonomous Vehicle [slides.pdf], [recorded video]
    Dongkyu Jung (Kyungpook National University, Korea (South)); Daejin Park (Kyungpook National University (KNU), Korea (South)) 

1-B: Special Session: FPGA Technologies for Adaptive Computing – I

Monday, December 20, 15:30 – 16:30 (Singapore time: GMT+8)
Session chair: Fujieda Naoki (AIT, Japan) (TBC)
Room: Room-2, Zoom Link (TBC)

  • 15:30   Host Bypassing: Direct Data Piping from the Network to the Hardware Accelerator  [slides.pdf], [recorded video]
    Ralf Kundel (Technical University of Darmstadt, Germany); Kadir Eryigit (Zoi TechCon GmbH, Germany); Jonas Markussen (Dolphin Interconnect Solutions & Simula Research Laboratory, Norway); Carsten Griwodz (Universitetet i Oslo & SimulaMet, Norway); Osama Abboud (Huawei Technologies Dusseldorf GmbH, Germany); Rhaban Hark and Ralf Steinmetz (Technische Universität Darmstadt, Germany)
  • 15:50   A function-rich FPGA system of camera image processing for video meeting  [slides.pdf], [recorded video]
    Takashi Odan, Takuto Kanamori and Kenji Kise (Tokyo Institute of Technology, Japan)
  • 16:10   RVCoreP-32IC: An optimized RISC-V soft processor supporting the compressed instructions [slides.pdf], [recorded video]
    Takuto Kanamori and Kenji Kise (Tokyo Institute of Technology, Japan) 

2-A: Multicore/Manycore SoC Programming and Real-time Systems

Monday, December 20, 16:40 – 18:00 (Singapore time: GMT+8)
Session chair: Yi-Chung Chen
(SUNY, USA) (TBC)
Room: Room-1
, Zoom Link (TBC)

  • 16:40   Execution Right Delegation Scheduling Algorithm for Multiprocessor [slides.pdf], [recorded video]
    Takaharu Suzuki (Japan Advanced Institute of Science and Technology, Japan)
  • 17:00   SIMD Parallel Execution on GPU from High-Level Dataflow Synthesis [slides.pdf], [recorded video]
    Aurelien Bloch (EPFL STI-SCI-MM, Switzerland); Simone Casale Brunet (EPFL & SCI STI MM, Switzerland); Marco Mattavelli (EPFL, Switzerland)
  • 17:20   Scheduling DAGs of Multi-version Multi-phase Tasks on Heterogeneous Real-time Systems[slides.pdf], [recorded video]
    Julius Roeder, Benjamin Rouxel and Clemens Grelck (University of Amsterdam, The Netherlands)
  • 17:4 0   Performance Estimation of High-Level Dataflow Program on Heterogeneous Platforms[slides.pdf], [recorded video]
    Aurelien Bloch (EPFL STI-SCI-MM, Switzerland); Simone Casale Brunet (EPFL & SCI STI MM, Switzerland); Marco Mattavelli (EPFL, Switzerland) 

2-B: Special Session: FPGA Technologies for Adaptive Computing- II

Monday, December 20, 16:40 – 18:00 (Singapore time: GMT+8)
Session chair:
Fujieda Naoki (AIT, Japan) (TBC)
Room: Room-2
, Zoom Link (TBC)

  • 16:40   Parallel Implementation of CNN on Multi-FPGA Cluster[slides.pdf], [recorded video]
    Yasuyu Fukushima, Kensuke Iizuka and Hideharu Amano (Keio University, Japan) 
  • 17:06   A low cost and portable mini motor car system with a BNN accelerator on FPGA [slides.pdf], [recorded video]
    Fumio Hamanaka, Takuto Kanamori and Kenji Kise (Tokyo Institute of Technology, Japan)
  • 17:33   A Memory-Access-Minimized BCNN Accelerator Using Nonvolatile FPGA with Only-Once-Write Shifting [slides.pdf], [recorded video]
    Daisuke Suzuki (The University of Aizu, Japan); Takahiro Oka and Takahiro Hanyu (Tohoku University, Japan) 

3-A: Algorithms, Architecture, and Hardware Acceleration for AI on the Edge – I

Tuesday, December 21, 15:00 – 16:20 (Singapore time: GMT+8)
Session chair:
Lan-Da Van (NCTU, Taiwan) and Yeong-Kang Lai (NCHU, Taiwan) (TBC)
Room: Room-1
, Zoom Link (TBC)

  • 15:00   Multi-objective Reinforcement Learning for Energy Harvesting Wireless Sensor Nodes [slides.pdf], [recorded video]
    Shaswot Shresthamali and Masaaki Kondo (Keio University, Japan); Hiroshi Nakamura (The University of Tokyo, Japan)

    15:20   MSCU: Accelerating CNN Inference with Multiple Sizes of Compute Unit on FPGAs
    [slides.pdf], [recorded video]
    Bao Zhenshan, Guo Junnan, Li Xiaqing and Zhang Wenbo (Beijing University of Technology, China)
  • 15:40   Variable Bit-Precision Vector Extension for RISC-V Based Processors [slides.pdf], [recorded video]
    Risikesh R k (International Institute of Information Technology Bangalore, India); Sharad Sinha (Indian Institute of Technology Goa, India); Nanditha Rao (IIIT Bangalore, India)
  • 16:00   Parasitic-Aware Modelling for Neural Networks Implemented with Multi-level Memristor Crossbar Array [slides.pdf], [recorded video]
    Tiancheng Cao (Nanyang Technological University, Singapore); Chen Liu (Agency for Science, Technology and Research, Singapore); Yuan Gao (Institute of Microelectronics, A*STAR, Singapore); Wang Ling Goh (Nanyang Technological University, Singapore)

3-B: Special Session: Emerging Machine Learning and Deep Learning Models: Theory and Applications – I

Tuesday, December 21, 15:00 – 16:20 (Singapore time: GMT+8)
Session chair:
Jungpil Shin (Univ. of Aizu, Japan) (TBC)
Room: Room-2
, Zoom Link (TBC)

  •  15:00   Distributed Neural Network with TensorFlow on Human Activity Recognition over Multicore TPU [slides.pdf], [recorded video]
    Incheon Paik (The University of Aizu, Japan); Haklin Kimm (East Stroudsburg University, USA)
  • 15:20 EEG-based Positive-Negative Emotion Classification using Machine Learning Techniques [slides.pdf], [recorded video]
    Yuta Kasuga and Jungpil Shin (University of Aizu, Japan); Md. Rabiul Islam and Md. Al Mehedi Hasan (Pattern Processing Lab, Japan); Yuichi Okuyama and Yoichi Tomioka (University of Aizu, Japan)
  • 15:40   CNN-based End-to-end Autonomous Driving on FPGA Using TVM and VTA [slides.pdf], [recorded video]
    Toshihiro Uetsuki (University of Aizu, Japan); Yuichi Okuyama (The University of Aizu, Japan); Jungpil Shin (University of AIZU, Japan) 
  • 16:00   Surface Type Classification for Autonomous Robots Using Temporal, Statistical and Spectral Feature Extraction and Selection [slides.pdf], [recorded video]
    Md. Al Mehedi Hasan (Pattern Processing Lab, Japan); Fuad Al Abir (Rajshahi University of Engineering & Technology, Bangladesh); Jungpil Shin (University of Aizu, Japan)

4-A: Algorithms, Architecture, and Hardware Acceleration for AI on the Edge – II

Tuesday, December 21, 16:30 – 17:50 (Singapore time: GMT+8)
Session chair:
Lan-Da Van (NCTU, Taiwan) and Yeong-Kang Lai (NCHU, Taiwan) (TBC)
Room: Room-1
, Zoom Link (TBC)

  •  16:30   A Multi-scale Binarized Neural Network Application based on All programmable System on Chip [slides.pdf], [recorded video]
    Maoyang Xiang (8 Somapah Rd & Singapore University Technology and Desgin, Singapore); T. Hui Teo (Singapore University of Technology and Design, Singapore)

  • 16:50   Data Fusion Driven Lane-level Precision Data Transmission for V2X Road Applications [slides.pdf], [recorded video]
    Albert Budi Christian (National Yang Ming Chiao Tung University, Taiwan); Chih-Yu Lin (National Taiwan Ocean University, Taiwan); Lan-Da Van (National Yang Ming Chiao Tung University, Taiwan); Yu-Chee Tseng (National Yang Ming Chiao Tung University, Taiwan)

  • 17:10   A Heterogeneous Full-stack AI Platform for Performance Monitoring and Hardware-specific Optimizations [slides.pdf], [recorded video]
    Zikang Zhou, Chao Fu and Ruiqi Xie (State Key Lab of ASIC & System, Fudan University, China); Jun Han (State Key Lab of ASIC & System, Fudan University, China)

  • 17:30   A Computation-Aware TPL Utilization Procedure for Parallelizing the FastICA Algorithm on a Multi-Core CPU [slides.pdf], [recorded video]
    Lan-Da Van and Tao Jung Wang (National Yang Ming Chiao Tung University, Taiwan); Sing-Jia Tzeng (National Yang Ming CHiao Tung University, Taiwan); Tzyy-ping Jung (UCSD, USA)

4-B: Special Session: Emerging Machine Learning and Deep Learning Models: Theory and Applications – II

Tuesday, December 21, 16:30 – 17:50 (Singapore time: GMT+8)
Session chair:
Jungpil Shin (Univ. of Aizu, Japan) (TBC)
Room: Room-2
, Zoom Link (TBC)

  • 16:30   A Distance Estimation Method to Railway Crossing Using Warning Signs [slides.pdf], [recorded video]
    Kaisei Shimura (The University of Aizu, Japan); Yoichi Tomioka (University of Aizu, Japan); Zhao Qiangfu (The University of Aizu, Japan)

  • 16:50   Dynamic Service Recommendation Using Lightweight BERT-based Service Embedding in Edge Computing [slides.pdf], [recorded video]
    Kungan Zeng (University of Aizu, Japan); Incheon Paik (The University of Aizu, Japan)
  • 17:10   Light-weight Enhanced Semantics-Guided Neural Networks for Skeleton-Based Human Action Recognition [slides.pdf], [recorded video]
    Hongbo Chen (Aizu University, Japan); Lei Jing (University of Aizu, Japan)
  • 17:30   Ising-based Combinatorial Clustering using the Kernel Method [slides.pdf], [recorded video]
    Masahito Kumagai, Kazuhiko Komatsu, Masayuki Sato and Hiroaki Kobayashi (Tohoku University, Japan)

5-A: Special Session: Secure, Reliable, and Energy-efficient Execution on MPSoCs

Wednesday, December 22, 9:00 – 10:20 (Singapore time: GMT+8)
Session chair:
Alok Prakesh (NTU, Singapore) and Amit Kumar Singh (Univ. of Essex, UK) (TBC)
Room: Room-1
, Zoom Link (TBC)

  • 9:00     FPGA based Adaptive Hardware Acceleration for Multiple Deep Learning Tasks [slides.pdf], [recorded video]
    Yufan Lu, Xiaojun Zhai, Sangeet Saha, Shoaib Ehsan and Klaus McDonald-Maier (University of Essex, United Kingdom (Great Britain))

  • 9:20     Detection of Cache Side Channel Attacks using Thread Level Monitoring of Hardware Performance Counters [slides.pdf], [recorded video]
    Pavitra Prakash Bhade and Sharad Sinha (Indian Institute of Technology Goa, India)
  • 9:40     2QoSM: A Q-Learner QoS Manager for Application-Guided Power-Aware Systems [slides.pdf], [recorded video]
    Michael J Giardino (ETH Zürich, Switzerland); Daniel Schwyn (ETH Zurich, Switzerland); Bonnie Ferri and Aldo A. Ferri (Georgia Institute of Technology, USA)
  • 10:00   Trends and Challenges in Ensuring Security for Low Power and High-Performance Embedded SoCs [slides.pdf], [recorded video]
    Parisa Rahimi and Amit Kumar Singh (University of Essex, United Kingdom (Great Britain)); Xiaohang Wang (South China University of Technology, China); Alok Prakash (Nanyang Technological University, Singapore)

5-B: Special Session: Auto-Tuning for Multicore and GPU

Wednesday, December 22, 9:00 – 10:20 (Singapore time: GMT+8)
Session chair:
Masahiro Nakao (RIKEN R-CCS, Japan) (TBC)
Room: Room-2
, Zoom Link (TBC)

  • 9:00  Task Scheduling Strategies for Batched Basic Linear Algebra Subprograms on Many-core CPUs [slides.pdf], [recorded video]
    Daichi Mukunoki (RIKEN Center for Computational Science, Japan); Yusuke Hirota (University of Fukui, Japan); Toshiyuki Imamura (RIKEN & Advanced Institute for Computational Science, Japan)
  • 9:20     Portability of Vectorization-aware Performance Tuning Expertise across System Generations [slides.pdf], [recorded video] 
    Shunpei Sugawara and Yoichi Shimomura (Tohoku University, Japan); Ryusuke Egawa (Tohoku University Japan, Japan); Hiroyuki Takizawa (Tohoku University, Japan)
  • 9:40     Enhancing Autotuning Capability with a History Database [slides.pdf], [recorded video]
    Younghyun Cho (University of California, Berkeley, USA); James Demmel (UC Berkeley, USA); Xiaoye Sherry Li, Yang Liu and Hengrui Luo (Lawrence Berkeley National Laboratory, USA)
  • 10:00   Sparse matrix ordering method with a quantum annealing approach and its parameter tuning [slides.pdf], [recorded video]
    Tomoko Komiyama and Tomohiro Suzuki (University of Yamanashi, Japan)

6-A: Special Session: Low-power and Solutions for Future SoC design

Wednesday, December 22, 10:30 – 11:30  (Singapore time: GMT+8)
Session chair:
Akram Ben Ahmed (AIST, Japan) and Hayate Okuhara (UNIBO, Italy) (TBC)
Room: Room-1
, Zoom Link (TBC)

  • 10:30   A Highly Efficient Layout-Aware FPGA Overlay Accelerator Mapping Method [slides.pdf], [recorded video]
    Tanvir Ahmed (Edgecortix, Inc., Japan); Johannes Maximilian Kühn (Preferred Networks Inc., Japan); Ken Namura (Preferred Networks, Inc., Japan)
  • 10:50   Energy saving in a multi-context coarse grained reconfigurable array with non-volatile flip-flops [slides.pdf], [recorded video]
    Aika Kamei, Takuya Kojima and Hideharu Amano (Keio University, Japan); Daiki Yokoyama, Hisato Miyauchi and Kimiyoshi Usami (Shibaura Institute of Technology, Japan); Keizo Hiraga (Sony, Japan); Kenta Suzuki and Kazuhiro Bessho (Sony Semiconductor Solutions Corporation, Japan)
     
  • 11:10   Multiport Register File Design for High-Performance Embedded Cores [slide.pdf],[recorded video]
    Junichiro Kadomoto (University of Tokyo, Japan); Hidetsugu Irie and Shuichi Sakai (The University of Tokyo, Japan)

6-B: Special Session: Intelligent Systems and Learning Technologies: Models, Methods, and Applications – I

Wednesday, December 22, 10:30 – 11:30  (Singapore time: GMT+8)
Session chair:
Mohamed Hamada (Univ. of Aizu, Japan) and Sarika Jain (NITKKR, India) (TBC)
Room: Room-2
, Zoom Link (TBC)

  • 10:30   Text compression based on an alternative approach of run-length coding using Burrows-Wheeler transform and arithmetic coding [slides.pdf], [recorded video]
    Md. Atiqur Rahman (the University of Aizu, Japan); Mohamed Hamada (UoA, Japan); Md Rahman (Islamic University Bangladesh, Bangladesh)

  • 10:50   UI Method to Support Knowledge Creation in Hybrid Museum Experience  [slides.pdf], [recorded video]
    Toru Tamahashi (The University of Aizu, Japan); Rentaro Yoshioka (University of Aizu, Japan); Takayuki Hoshino (The University of AIZU & Nihon Unisys, Ltd., Japan)
  • 11:10   Design of a Knowledge Experience based Environment for Museum Data Exploration and Knowledge Creation [slides.pdf], [recorded video]
    Takayuki Hoshino (The University of AIZU & Nihon Unisys, Ltd., Japan); Rentaro Yoshioka (University of Aizu, Japan); Yukihide Kohira (The University of Aizu, Japan)

7-A: Embedded Neuromorphic Computing Systems

Wednesday, December 22, 16:10 – 17:30 (Singapore time: GMT+8)
Session chair:
 Charlotte Frenkel (UCLouvain, Belgium) and Gianvito Urgese (PoliTO, Italy) (TBC)
Room: Room-1
, Zoom Link (TBC)

  • 16:10   Mini-Batch Training along Convolution Windows for Representation Learning Based on Spike-Time-Dependent-Plasticity Rule [slides.pdf], [recorded video]
    Yohei Shimmyo (University of Aizu, Japan); Yuichi Okuyama (The University of Aizu, Japan)

  • 16:30   Performance Comparision of TPU, GPU, CPU on Google Colaboratory over Distributed Deep Learning [slides.pdf], [recorded video]
    Haklin Kimm (East Stroudsburg University, USA); Incheon Paik (The University of Aizu, Japan); Hanke Kimm (Stonybrook University, USA)
  • 16:50   A Network Simulator for the Estimation of Bandwidth Load and Latency created by Heterogeneous Spiking Neural Networks on Neuromorphic Computing Communication Networks [slides.pdf], [recorded video]
    Robert Kleijnen (Forschungszentrum Jülich GmbH, Germany); Markus Robens (Forschungszentrum Juelich GmbH, Germany); Michael Schiek (Forschungszentrum Jülich, Germany); Stefan van Waasen (Forschungszentrum Jülich GmbH, Germany)
  • 17:10   Configuring an Embedded Neuromorphic coprocessor using a RISC-V chip for enabling edge computing applications [slides.pdf], [recorded video]
    Evelina Forno, Andrea Spitale and Enrico Macii (Politecnico di Torino, Italy); Gianvito Urgese (Politecnico Di Torino, Italy)

7-B: Special Session: Intelligent Systems and Learning Technologies: Models, Methods, and Applications – II

Wednesday, December 22, 16:10 – 17:30 (Singapore time: GMT+8)
Session chair:
Mohamed Hamada (Univ. of Aizu, Japan) and Sarika Jain (NITKKR, India) (TBC)
Room: Room-2
, Zoom Link (TBC)

  • 16:10   Evaluation of Recursive Feature Elimination and LASSO Regularization based optimized feature selection approaches for cervical cancer prediction [slides.pdf], [recorded video]
    Mohamed Hamada (UoA, Japan); Jesse Jeremiah Tanimu and Mohammed Hassan (Bayero University, Kano, Nigeria); Habeebah Kakudi (University of Malaya, Malaysia); Patience Robert (Federal Polytechnic, Bali, Nigeria)
  • 16:30   The Role of Linear Discriminant Analysis for Accurate Prediction of Breast Cancer  [slides.pdf], [recorded video]
    Egwom Jessica (Bayero University, Kano, Nigeria); Mohamed Hamada (UoA, Japan); Saratu Ilu (Bayero University, Nigeria); Mohammed Hassan (Bayero University, Kano, Nigeria)
  • 16:50   An Intelligent Plant Dissease Detection System for Smart Hydroponic using Convolutional Neural Network  [slides.pdf], [recorded video]
    Aminu Musa (Federal University Dutse, Nigeria); Mohamed Hamada (UoA, Japan); Farouq Muhammad Aliyu (King Fahd University of Petroleum and Minerals, Saudi Arabia); Mohammed Hassan (Bayero University, Kano, Nigeria)

  • 17:10   A Framework and Its User Interface to Learn Machine Learning Models [slides.pdf], [recorded video]
    Atsushi Takamiya and Md. Mostafizer Rahman (The University of Aizu, Japan); Yutaka Watanobe (University of Aizu, Japan)

8-A: Multicore/Manycore SoC Architectures and Interconnects

Thursday, December 23, 9:00 – 10:20 (Singapore time: GMT+8)
Session chair:
José L. Abellán (UCAM, Spain) and Chun-Ming Huang (TSRI, Taiwan) (TBC)
Rooms: Room-1
, Zoom Link (TBC)

  • 9:00     Boosting CPU Performance using Pipelined Branch and Jump Folding Hardware with Turbo Module [slides.pdf], [recorded video]
    Mong Sim (University of Colorado Colorado Springs, USA)

  • 9:20     Efficient resource shared RISC-V multicore processor [slides.pdf], [recorded video]
    Md Islam and Kenji Kise (Tokyo Institute of Technology, Japan)
  • 9:40     Task-level Redundancy vs Instruction-level Redundancy against Single Event Upsets in Real-time DAG scheduling [slides.pdf],[recorded video]
    Lukas Miedema, Benjamin Rouxel and Clemens Grelck (University of Amsterdam, The Netherlands)
  • 10:00   RELAX: A REconfigurabLe ApproXimate Network-on-Chip [slides.pdf], [recorded video]
    Richard Fenster (Concordia University, Canada); Sébastien Le Beux (Ecole Centrale de Lyon, Canada)

9-A: Operating System Platform and Real-time Embedded Applications

Thursday, December 23, 10:30 – 11:30 (Singapore time: GMT+8)
Session chair:
Shinobu Miwa (UEC, Japan) (TBC)
Rooms: Room-1
, Zoom Link (TBC)

  • 10:30   Analyzable Publish-Subcribe Communication through a Wait-Free FIFO Channel for MPSoC Real-Time Applications [slides.pdf], [recorded video]
    Saeid Dehnavi (Eindhoven University of Technology (TU/e), The Netherlands); Dip Goswami (Eindhoven University of Technology, Netherlands, The Netherlands); Kees Goossens (Eindhoven University of Technology, The Netherlands)
  • 10:50 LUSH: Lightweight Framework for User-level Scheduling in Heterogeneous Multicores [slides.pdf], [recorded video]
    Vasco Miguel Liang Xu, Liam White McShane, and  Daniel Mossé (University of Pittsburgh, USA)
  • 11:10   An Architecture to Enable Machine-Learning-Based Task Migration for Multi-Core Real-Time Systems [slides.pdf],[recorded video] 
    Octavio Ivan Delgadillo Ruiz (Fortiss GmbH & Technical University of Munich, Germany); Bernhard Blieninger and Juri Kuhn (Fortiss GmbH, Germany); Uwe Baumgarten (Technical University of Munich, Germany)