Keynote Speakers

On-Chip Epilepsy Detection: Where Machine Learning Meets Patient-Specific Wearable Healthcare

Jerald Yoo, National University of Singapore, Singapore.

Abstract: Epilepsy is a severe and chronic neurological disorder that affects over 65 million people worldwide. Yet current seizure/epilepsy detection and treatment mainly rely on a physician interviewing the subject, which is not effective in infant/children group. Moreover, patient-to-patient and age-to-age variation on seizure pattern from surface EEG makes such detection particularly challenging. To expand the beneficiary group to even infants and also to effectively adapt to each patient, a wearable form-factor, the patient-specific system with machine learning is of crucial. However, the wearable environment is challenging for circuit designers due to unstable skin-electrode interface, large mismatch, and static/dynamic offset.
This talk will cover the design strategies of patient-specific epilepsy detection System-on-Chip (SoC). We will first explore the difficulties, limitations, and potential pitfalls in wearable interface circuit design and approaches to overcome such issues. We will cover various IA circuit topologies and their key metrics to deal with offset compensation. Several state-of-the-art instrumentation amplifiers that emphasize on different parameters will also be discussed. Moving on, we will explore the feature extraction and the patient-specific classification using Machine Learning technique. Comparison of different algorithms under limited training sets will be made. Finally, an on-chip epilepsy detection and recording SoC will be presented, which integrates all the components covered during the talk. The talk will conclude with interesting aspects and opportunities that lie ahead.

Biography: Jerald Yoo received the B.S., M.S., and Ph.D. degrees in the Department of Electrical Engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively.
From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. From 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Since 2017, he has been with the Department of Electrical and Computer Engineering, National University of Singapore, Singapore, where he is currently an Associate Professor. He has pioneered researches on low-energy body-area-network (BAN) transceivers and wearable body sensor networks using the planar-fashionable circuit board for a continuous health monitoring system. He authored book chapters in Biomedical CMOS ICs (Springer, 2010) and in Enabling the Internet of Things—From Circuits to Networks (Springer, 2017). His current research interests include low-energy circuit technology for wearable bio-signal sensors, flexible circuit board platform, BAN transceivers, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT) and System-on-Chip (SoC) design to system realization for wearable healthcare applications.
Dr. Yoo served as an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer (2019-2021) as well as an IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer (2017-2018). He is the recipient or a co-recipient of several awards: IEEE International Solid-State Circuits Conference (ISSCC) 2020 Demonstration Session Award (Certificate of Recognition), IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015 and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the founding vice-chair of IEEE SSCS United Arab Emirates (UAE) Chapter, and currently is the chair of the IEEE SSCS Singapore Chapter. Currently, he serves as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), ISSCC Student Research Preview (co-chair), and IEEE Asian Solid-State Circuits Conference (A-SSCC, Emerging Technologies and Applications Subcommittee Chair). He also served as the subcommiteee chair at IEEE Custom Integrated Circuits Conference (CICC). He is also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society, and an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems as well as IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS). He is a senior member of IEEE.

The Growing RISC-V Ecosystem and Opportunities Ahead for SoC

Chin Hu Ong, StarFive, China.

Abstract: The open standard instruction set architecture (ISA) known as RISC-V that began at UC Berkeley in 2010 is quickly becoming mainstream. Semico Research predicts the market will consume 62.4 billion RISC-V CPU cores by 2025, a 146.2% CAGR from  2018 to 2025. More and more companies are turning to RISC-V solutions for a wide variety of applications and to address a wide range of performance and volume requirements. However, there are some individuals who are not aware of why RISC-V is so compelling. This talk will cover the compelling value proposition of RISC-V and why the RISC-V technology has been experiencing tremendous growth and market acceptance across multiple industries and academia. The talk will provide some of the latest industry trends and key use cases of RISC-V in the area of IoT, embedded, computing, data center, artificial intelligence/machine learning, and autonomous driving.
The talk will explore how the Scalable RISC-V architecture is able to address the many-core SOC (MCSoC) challenges. To enhance scalability, novice approach like packetized networks are not just used for data communication but also for control communication which travels on the die and across dies. Besides, the talk will cover the RISC-V Platform Work Group’s work on various scalable platform specifications including scalable IOMMU, Advanced Interrupt Architecture (AIA) that can scale from single-core up to many cores with virtual machines/IO support.
Moving on, the talk will discuss RISC-V low power design opportunities in the core and SoC levels. With concise ISA and selectable extensions, RISC-V cores can be optimized to deliver better power performance. In addition, RISC-V allows custom functions to be implemented and executed directly in cores’ instruction pipelines which would provide further performance per watts advantages over external solutions. On the SoC/Platform level, RISC-V specifications are agnostic to the platform’s power architecture and hence, allow common low power techniques likes dynamic clock gating, per core and per CPU cluster power controls, dynamic voltage/frequency scaling (DVFS), adaptive voltage scaling (AVS) and so on to be implemented.  In terms of software, RISC-V SoCs can be designed to take advantage of established standards like ACPI, SCMI, different Linux schedulers, etc.  In fact, the opportunities of implementing energy-efficient RISC-V SoCs have been well demonstrated with numerous low-power products in the market ranging from micro-controllers for small IoT devices to SoCs with thousands of cores for AI/ML applications.
Finally, we will explore the RISC-V software philosophy and some ongoing efforts by the RISC-V community in ensuring standard Linux scheduler (Energy Aware Scheduling and Capacity Aware Scheduling) works seamlessly for RISC-V. This further strengthens RISC-V solution to take advantage of heterogeneous multicore design (both hardware and software) for achieving the best performance per watt, which is further enhanced through customizing RISC-V extensions. The high growth rate of open source software adopting RISC-V platform also makes the transition of various today’s solutions to RISC-V seamless, while enjoying better performance due to RISC-V openness to architecture and software definitions.
The talk will conclude with interesting aspects and opportunities that lie ahead for the RISC-V world.

Biography: Chin Hu Ong received his B.Eng. from University of Technology Malaysia (UTM) in 2001. He later received his MBA from Nottingham Trent University in 2008. He also did undergo the Harvard Business School’s ManageMentor® Course in 2013. Chin Hu is a Senior Member of IEEE. He has published multiple papers in IEEE Asian Test Symposium in China and Japan. He is also a Certified Practitioner of NLP (Neuro Linguistic Programming) from American Board of NLP.
Chin Hu started his career at the newly setup Agilent Technologies Hardcopy ASIC Design Centre in Penang as ASIC Design Engineer. He was relocated to Oregon, USA for a year in 2001. From 2004 to 2006, he was leading the DFT team and Artwork Verification team at Agilent Technologies and Avago Technologies (currently known as Broadcom). He successfully taped-out multiple 130nm production ASICs and 90nm testchip. From 2013 to 2017, he was the Malaysia Site Director at Marvell Semiconductor whereby he managed the Marvell Design Center in Penang & a remote team in Tokyo for the development of ARM based ASIC & SoC for the consumer and enterprise electronics products. He led the team to successfully taped out ~10 SoC (from 130nm to 28nm) targeted for consumer imaging, printer, mobile phone, security camera and consumable security application for customers in China, Japan, Singapore, Taiwan, and USA.
In 2017, Chin Hu joined Intel Programmable Solutions Group (PSG) as Engineering Director where he led the IP Solutions design organization that drives IP & Platform Solutions strategy & roadmap, IPs & Subsystem portfolio planning and IP & Platform development for the Intel FPGA group. In PSG, he led the team to deliver cutting edge IP solution for 14nm and 10nm FPGA products both in the form of silicon hard IPs and FPGA soft IPs including HBM controller, DDR4 controller, customize PCIe Gen4 controller, 10/25Gb Ethernet, 10GbE-400GbE 1588 PTP, CPRI MAC and PHY, eCPRI, ORAN, high speed serial interconnect like Interlaken and Serialite4 etc.
In May 2021, Chin Hu joined StarFive Technology as the VP and GM. He built the StarFive Technology Malaysia organization from the ground-up and successfully built an experienced IC Design and Software development engineering team within a short period of time.. He is currently leading the StarFive Malaysia Design Center to focus on developing differentiated IPs & Subsystems, RISC-V SoC and Software for the RISC-V ecosystem.