{"id":11216,"date":"2026-02-01T23:56:03","date_gmt":"2026-02-01T23:56:03","guid":{"rendered":"https:\/\/mcsoc-forum.org\/site\/?page_id=11216"},"modified":"2026-03-09T02:32:50","modified_gmt":"2026-03-09T02:32:50","slug":"neurocore-t16","status":"publish","type":"page","link":"https:\/\/mcsoc-forum.org\/site\/index.php\/neurocore-t16\/","title":{"rendered":"3D Integrated and Heterogeneous Neuromorphic"},"content":{"rendered":"\n
\"\"<\/figure>\n\n\n\n

\n \n \u2190 Back to the NeuroCore 2026 Page\n <\/a>\n<\/p>\n

\n\n

Track Chair<\/h2>\n
\n
\"Dr.<\/figure>

Xabier Iturbe<\/a><\/strong>
IK4-Ikerlan Research Alliance, Spain<\/span><\/p>\n<\/div><\/div>\n<\/div>\n\n\n\n

Call for Papers<\/h3>\n\n\n\n

Neuromorphic computing is rapidly advancing toward architectures that demand unprecedented levels of integration density, interconnect bandwidth, and functional diversity. This track focuses on emerging technologies that enable scalable, high\u2011performance neuromorphic systems through 3D integration, chiplet\u2011based design, and heterogeneous integration of analog, digital, and novel device technologies. The track welcomes contributions that explore new materials, fabrication techniques, packaging strategies, and system\u2011level architectures that push the boundaries of how neuromorphic intelligence can be physically realized. Submissions may address device\u2011level innovations, circuit and architecture co\u2011design, integration methodologies, or full\u2011system demonstrations.<\/p>\n\n\n\n

Topics of Interest include, but are not limited to:<\/strong><\/h3>\n\n\n\n
    \n
  • 3D Integration for Neuromorphic Systems<\/strong>\n
      \n
    • 3D stacking of compute, memory, and sensor layers<\/li>\n\n\n\n
    • Through\u2011silicon vias (TSVs), hybrid bonding, and wafer\u2011level integration<\/li>\n\n\n\n
    • Thermal management and reliability in vertically integrated neuromorphic chips<\/li>\n<\/ul>\n<\/li>\n\n\n\n
    • Chiplet\u2011Based Neuromorphic Architectures<\/strong>\n
        \n
      • Interposer\u2011based and advanced packaging solutions<\/li>\n\n\n\n
      • High\u2011bandwidth, low\u2011latency interconnects for neuromorphic chiplet ecosystems<\/li>\n\n\n\n
      • Modular and scalable neuromorphic system design using chiplets<\/li>\n<\/ul>\n<\/li>\n\n\n\n
      • Heterogeneous Integration of Mixed\u2011Signal and Emerging Devices<\/strong>\n
          \n
        • Co\u2011integration of analog, digital, and mixed\u2011signal neuromorphic circuits<\/li>\n\n\n\n
        • Integration of emerging devices (RRAM, PCM, FeFETs, spintronics, photonics, etc.)<\/li>\n\n\n\n
        • Hybrid CMOS\u2013non\u2011CMOS neuromorphic platforms<\/li>\n<\/ul>\n<\/li>\n\n\n\n
        • System\u2011Level Design and Co\u2011Optimization<\/strong>\n
            \n
          • Architecture\u2013technology co\u2011design for 3D and heterogeneous neuromorphic systems<\/li>\n\n\n\n
          • Communication fabrics, routing strategies, and memory hierarchies<\/li>\n\n\n\n
          • Power, performance, and area optimization for integrated neuromorphic platforms<\/li>\n<\/ul>\n<\/li>\n\n\n\n
          • Fabrication, Packaging, and Test<\/strong>\n
              \n
            • Advanced packaging for neuromorphic accelerators<\/li>\n\n\n\n
            • Wafer\u2011scale integration and large\u2011area neuromorphic systems<\/li>\n\n\n\n
            • Testing, characterization, and benchmarking of 3D\/heterogeneous neuromorphic hardware<\/li>\n<\/ul>\n<\/li>\n\n\n\n
            • Applications and Demonstrations<\/strong>\n
                \n
              • End\u2011to\u2011end neuromorphic systems leveraging 3D or heterogeneous integration<\/li>\n\n\n\n
              • Real\u2011world workloads: robotics, edge AI, sensory processing, autonomous systems<\/li>\n\n\n\n
              • Benchmarks, datasets, and evaluation methodologies<\/li>\n<\/ul>\n<\/li>\n<\/ul>\n\n\n\n