{"id":11364,"date":"2026-02-04T00:16:01","date_gmt":"2026-02-04T00:16:01","guid":{"rendered":"https:\/\/mcsoc-forum.org\/site\/?page_id=11364"},"modified":"2026-02-04T01:42:23","modified_gmt":"2026-02-04T01:42:23","slug":"neurocore-t1","status":"publish","type":"page","link":"https:\/\/mcsoc-forum.org\/site\/index.php\/neurocore-t1\/","title":{"rendered":"Brain\u2011Inspired and Neuromorphic System Architectures"},"content":{"rendered":"\n
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\n \n \u2190 Back to the NeuroCore 2026 Page\n <\/a>\n<\/p>\n

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Track Chair<\/h2>\n
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\"Amirreza<\/figure>

Amirreza Yousefzadeh<\/a><\/strong>
University of Twente, The Netherlands<\/span><\/p>\n<\/div><\/div>\n<\/div>\n\n\n\n

Call for Papers:\u202f\u202fBrain\u2011Inspired and Neuromorphic System Architectures<\/mark><\/strong><\/h2>\n\n\n\n

Brain\u2011inspired and neuromorphic computing aims to transcend the limitations of conventional architectures by embracing principles observed in biological neural systems\u2014massive parallelism, event\u2011driven signaling, sparse computation, adaptivity, and extreme energy efficiency. As emerging devices, memory technologies, and architectural paradigms mature, the field is rapidly evolving toward scalable, real\u2011time, and cognitively capable systems that operate far beyond the traditional von Neumann model.
This track focuses on innovations across the full architectural stack, from device\u2011level substrates and memory hierarchies to chip\u2011scale and system\u2011level designs that embody neural principles. We invite contributions that advance the theory, design, implementation, and evaluation of neuromorphic architectures, as well as cross\u2011layer approaches that tightly couple algorithms, circuits, and hardware platforms. Submissions that demonstrate practical systems, prototypes, or application\u2011driven neuromorphic deployments are especially encouraged. <\/p>\n\n\n\n

Topics of Interest include, but are not limited to:<\/strong><\/h3>\n\n\n\n

Brain\u2011Inspired and Neuromorphic Architectures<\/strong><\/h4>\n\n\n\n
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  • Event\u2011driven, asynchronous, and massively parallel architectures<\/li>\n\n\n\n
  • Spiking neural network (SNN) hardware platforms<\/li>\n\n\n\n
  • Cognitive, adaptive, and biologically inspired system models<\/li>\n<\/ul>\n\n\n\n

    Architectural Design and Hardware Platforms<\/strong><\/h4>\n\n\n\n
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    • Neuromorphic processors, accelerators, and heterogeneous SoCs<\/li>\n\n\n\n
    • Chiplet\u2011based, 3D\u2011stacked, and wafer\u2011scale neuromorphic systems<\/li>\n\n\n\n
    • Memory hierarchies and communication fabrics for neural workloads<\/li>\n<\/ul>\n\n\n\n

      Emerging Devices and Novel Substrates<\/strong><\/h4>\n\n\n\n
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      • RRAM, PCM, FeFETs, spintronics, photonics, and other emerging devices<\/li>\n\n\n\n
      • Device\u2011architecture co\u2011design for neuromorphic computation<\/li>\n\n\n\n
      • Analog and mixed\u2011signal neuromorphic circuits<\/li>\n<\/ul>\n\n\n\n

        In\u2011Memory and Near\u2011Memory Computing<\/strong><\/h4>\n\n\n\n
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        • Compute\u2011in\u2011memory (CIM) architectures for SNNs and sparse workloads<\/li>\n\n\n\n
        • Memory\u2011centric neuromorphic system design<\/li>\n\n\n\n
        • Algorithm\u2013memory co\u2011optimization<\/li>\n<\/ul>\n\n\n\n

          Hardware\u2013Software Co\u2011Design<\/strong><\/h4>\n\n\n\n
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          • Mapping neural models to neuromorphic substrates<\/li>\n\n\n\n
          • Compilers, programming models, and toolchains for neuromorphic systems<\/li>\n\n\n\n
          • Cross\u2011layer optimization for latency, energy, and robustness<\/li>\n<\/ul>\n\n\n\n

            System\u2011Level Integration and Demonstrations<\/strong><\/h4>\n\n\n\n
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            • End\u2011to\u2011end neuromorphic systems and prototypes<\/li>\n\n\n\n
            • Benchmarking, evaluation methodologies, and workload characterization<\/li>\n\n\n\n
            • Applications in robotics, sensing, autonomous systems, and cognitive agents<\/li>\n<\/ul>\n\n\n\n