{"id":299,"date":"2022-01-25T17:50:42","date_gmt":"2022-01-25T17:50:42","guid":{"rendered":"https:\/\/mcsoc-forum.org\/site\/?page_id=299"},"modified":"2026-02-18T07:40:31","modified_gmt":"2026-02-18T07:40:31","slug":"track-4","status":"publish","type":"page","link":"https:\/\/mcsoc-forum.org\/site\/index.php\/track-4\/","title":{"rendered":"Heterogeneous Integration and Advanced On-Chip Interconnects"},"content":{"rendered":"\n<div class=\"wp-block-group has-border-color has-medium-gray-border-color has-white-background-color has-background\" style=\"border-width:1px;border-radius:12px;padding-top:30px;padding-right:30px;padding-bottom:30px;padding-left:30px\">\n\n<h2 class=\"wp-block-heading has-text-color\" style=\"color:#00629b;text-transform:uppercase;letter-spacing:1px\">Track Chair<\/h2>\n<hr class=\"wp-block-separator has-text-color has-black-color has-alpha-channel-opacity has-black-background-color has-background is-style-wide\"\/>\n<div class=\"wp-block-media-text is-stacked-on-mobile\" style=\"margin-top:20px;margin-bottom:20px;grid-template-columns:15% auto\"><figure class=\"wp-block-media-text__media\"><img loading=\"lazy\" decoding=\"async\" width=\"150\" height=\"150\" src=\"http:\/\/mcsoc-forum.org\/site\/wp-content\/uploads\/2022\/01\/scholar-e1643363446774.jpg\" alt=\"TBC\" class=\"wp-image-176 size-full\"\/><\/figure><div class=\"wp-block-media-text__content\"><p class=\"has-large-font-size\"><strong>TBC<\/strong><\/p>\n<\/div><\/div>\n<\/div>\n\n\n\n<p>The rapid growth of AI, edge intelligence, and neuromorphic computing is pushing conventional monolithic CMOS architectures to their limits. The <strong>von Neumann bottleneck<\/strong>\u2014long the dominant constraint on compute efficiency\u2014now stands as the primary obstacle to achieving brain\u2011like parallelism and ultra\u2011low\u2011power processing. To overcome this barrier, the community is accelerating toward <strong>heterogeneous integration<\/strong>, <strong>3D architectures<\/strong>, and <strong>next\u2011generation on\u2011chip interconnect technologies<\/strong> that tightly couple compute, memory, and emerging device modalities.<\/p>\n\n\n\n<p>This track invites original contributions that explore the architectures, materials, packaging technologies, and circuit innovations enabling the next wave of high\u2011performance, energy\u2011efficient, and cognitively inspired systems.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Topics of Interest (include but are not limited to):<\/strong><\/h4>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>1. 3D Integration and Multi\u2011Modal Packaging<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li>3D chiplets, 2.5D\/3D packaging, and advanced heterogeneous integration<\/li>\n\n\n\n<li>EMIB, Foveros, hybrid bonding, and wafer\u2011level stacking<\/li>\n\n\n\n<li>Thermal, mechanical, and reliability challenges in deep 3D stacks<\/li>\n\n\n\n<li>Co\u2011design methodologies for multi\u2011modal integration (compute, memory, sensing)<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>2. Advanced On\u2011Chip Interconnects<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Scalable 2D\/3D Networks\u2011on\u2011Chip (NoCs) for many\u2011core and neuromorphic systems<\/li>\n\n\n\n<li>Photonic\u2011electronic interconnects and silicon photonics for high\u2011bandwidth, low\u2011latency communication<\/li>\n\n\n\n<li>Interconnect\u2011aware mapping, routing, and power optimization<\/li>\n\n\n\n<li>Fault\u2011tolerant and reliability\u2011driven interconnect architectures<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>3. Emerging Memory and Synaptic Devices<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Memristive, spintronic, ferroelectric, and phase\u2011change synapses<\/li>\n\n\n\n<li>Two\u2011terminal memristors and three\u2011terminal neuromorphic transistors<\/li>\n\n\n\n<li>Device\u2011circuit co\u2011design for in\u2011memory and near\u2011memory computing<\/li>\n\n\n\n<li>Variability, endurance, and scaling challenges in emerging NVM technologies<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>4. Neuromorphic and AI\u2011Centric Heterogeneous Architectures<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li>Integration of neuromorphic cores with digital logic and accelerators<\/li>\n\n\n\n<li>Multi\u2011modal compute substrates combining CMOS, RRAM, MRAM, PCM, and spintronics<\/li>\n\n\n\n<li>Event\u2011driven, massively parallel architectures inspired by biological computation<\/li>\n\n\n\n<li>Cross\u2011layer design for ultra\u2011low\u2011power AI and edge intelligence<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>5. Tools, Models, and Design Methodologies<\/strong><\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li>CAD\/EDA tools for 3D integration and heterogeneous packaging<\/li>\n\n\n\n<li>Modeling of thermal, electrical, and reliability behavior in stacked systems<\/li>\n\n\n\n<li>System\u2011level simulation frameworks for heterogeneous SoCs<\/li>\n\n\n\n<li>AI\u2011driven optimization for interconnect and packaging design<\/li>\n<\/ul>\n\n\n\n<h4 class=\"wp-block-heading\"><strong>Submission Guidelines<\/strong><\/h4>\n\n\n\n<p>Authors are invited to submit original, unpublished research manuscripts that align with the themes of this track. Submissions will undergo rigorous peer review based on technical quality, novelty, and relevance.<\/p>\n\n\n\n<h4 class=\"wp-block-heading\">Former Chairs<\/h4>\n\n\n\n<ul class=\"wp-block-list\">\n<li><strong><a href=\"https:\/\/drexel.edu\/engineering\/about\/faculty-staff\/T\/taskin-baris\/\">Prof. Baris Taskin<\/a><\/strong>, Drexel University, U.S.A. (2025)<\/li>\n\n\n\n<li><strong>Prof. Jos\u00e9 L. Abell\u00e1n<\/strong>, University of Murcia, Spain ( 2023 , 2024 )<\/li>\n<\/ul>\n","protected":false},"excerpt":{"rendered":"<p>Track Chair TBC The rapid growth of AI, edge intelligence, and neuromorphic computing is pushing conventional monolithic CMOS architectures to their limits. The von Neumann bottleneck\u2014long the dominant constraint on compute efficiency\u2014now stands as the primary obstacle to achieving brain\u2011like parallelism and ultra\u2011low\u2011power processing. To overcome this barrier, the community is accelerating toward heterogeneous integration, &hellip; <\/p>\n<p><a class=\"more-link btn\" href=\"https:\/\/mcsoc-forum.org\/site\/index.php\/track-4\/\">Continue reading<\/a><\/p>\n","protected":false},"author":1,"featured_media":0,"parent":0,"menu_order":0,"comment_status":"closed","ping_status":"closed","template":"","meta":{"footnotes":""},"class_list":["post-299","page","type-page","status-publish","hentry","nodate","item-wrap"],"_links":{"self":[{"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/pages\/299","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/pages"}],"about":[{"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/types\/page"}],"author":[{"embeddable":true,"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/comments?post=299"}],"version-history":[{"count":23,"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/pages\/299\/revisions"}],"predecessor-version":[{"id":11565,"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/pages\/299\/revisions\/11565"}],"wp:attachment":[{"href":"https:\/\/mcsoc-forum.org\/site\/index.php\/wp-json\/wp\/v2\/media?parent=299"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}