**We will keep adding slides as soon as we receive them from the authors.

Session 1: Auto-Tuning for Multicore and GPU (ATMG2019)

Distributed O(N) Linear Solver for Dense Symmetric Hierarchical Semi-Separable Matrices [slides.pdf]

Chenhan D. Yu (The University of Texas at Austin), Severin Reiz (Technische Universität München), George Biros (The University of Texas at Austin)

Optimization of Numerous Small Dense-Matrix–Vector Multiplications in H-Matrix Arithmetic on GPU [slides.pdf]

Satoshi Ohshima (Kyushu University), Ichitaro Yamazaki (University of Tennessee), Akihiro Ida (The University of Tokyo), Rio Yokota (Tokyo Institute of Technology)

An Automatic MPI Process Mapping Method Considering Locality and Memory Congestion on NUMA Systems [slides.pdf]

Mulya Agung (Tohoku University), Muhammad Alfian Amrizal (Tohoku University), Ryusuke Egawa (Tohoku University), Hiroyuki Takizawa (Tohoku University)

Performance Tuning of Tile Matrix Decomposition [slides.pdf]

Tomohiro Suzuki (University of Yamanashi)

Session 2: Low-power Solutions for Future SoC design

A System Delay Monitor Exploiting Automatic Cell-Based Design Flow and Post-Silicon Calibration [slides.pdf]

Hayate Okuhara (Keio University), Ryosuke Kazami (Keio University), Hideharu Amano (Keio University)

Multicore Power Estimation using Independent Component Analysis Based Modeling [slides.pdf]

Mark Sagi (Technical University of Munich), Nguyen Anh Vu Doan (Technical University of Munich), Thomas Wild (Technical University of Munich), Andreas Herkersdorf (Technical University of Munich)

Session 3-A: Digital Circuit & FPGA-based Design – I

FPGA/Python Co-Design for Lane Line Detection on a PYNQ-Z1 Board [slides.pdf]

Koki Honda (Keio University), Kaijie Wei (Keio University), Hideharu Amano (Keio University)

Design of Asynchronous CNN Circuits on Commercial FPGA from Synchronous CNN Circuits [slides.pdf]

Hayato Kato (The University of Aizu, Japan), Hiroshi Saito (The University of Aizu, Japan)

Modular Memory System for RISC-V Based MPSoCs on Xilinx FPGAs [slides.pdf]

Ahmed Kamaleldin (Technische Universität Dresden), Muhammad Ali (Technische Universität Dresden), Pedram Amini Rad (Technische Universität Dresden), Marcus Gottschalk (Technische Universität Dresden), Diana Göhringer (Technische Universität Dresden)

A Novel SLM-Based Virtual FPGA Overlay Architecture [slides.pdf]

Theingi Myint (Kumamoto University), Motoki Amagasaki (Kumamoto University), Qian Zhao (Kyushu Institute of Technology), Masahiro Iida (Kumamoto University), Masato Kiyama (Kumamoto University)

Session 3-B: Machine Learning

Deep Learning Framework with Arbitrary Numerical Precision [slides.pdf]

Masato Kiyama (Kumamoto University), Motoki Amagasaki (Kumamoto University), Masahiro Iida (Kumamoto University)

Tumour Detection using Convolutional Neural Network on a Lightweight Multi-Core Device [slides.pdf]

T. Hui Teo (Singapore University of Technology & Design), Wei Ming Tan (Singapore University of Technology & Design), Yi Shu Tan (Singapore University of Technology & Design)

Many Universal Convolution Cores for Ensemble Sparse Convolutional Neural Networks [slides.pdf]

Ryosuke Kuramochi (Tokyo Institute of Technology), Youki Sada (Tokyo Institute of Technology), Masayuki Shimoda (Tokyo Institute of Technology), Shimpei Sato (Tokyo Institute of Technology), Hiroki Nakahara (Tokyo Institute of Technology)

Distributed Neural Networks using TensorFlow over Multicore and Many-Core Systems [slides.pdf]

Jagadish Kumar Ranbirsingh (East Stroudsburg University), Hanke Kimm (East Stroudsburg University), Haklin Kimm (East Stroudsburg University)

Session 4-A: Digital Circuit & FPGA-based Design – II

An Efficient Implementation of a TAGE Branch Predictor for Soft Processors on FPGA [slides.pdf]

Katsunoshin Matsui (Tokyo Institute of Technology), Md Ashraful Islam (Tokyo Institute of Technology), Kenji Kise (Tokyo Institute of Technology)

Prototype of FPGA Dynamic Reconfiguration Based-on Context-Oriented Programming [slides.pdf]

Takeshi Ohkawa (Tokai University), Ikuta Tanigawa (Kyushu University), Mikiko Sato (Tokai University), Kenji Hisazumi (Kyushu University), Nobuhiko Ogura (Tokyo City University), Harumi Watanabe (Tokai University)

Implementation of Content-Based Anonymization Edge Router on NetFPGA [slides.pdf]

Akihiro Fukuhara (Keio University), Tomomu Iwai (Keio University), Yuiko Sakuma (Keio University), Hiroaki Nishi (Keio University)

Session 4-B: Intelligent Systems and Learning Technologies: Models, Methods, and Applications – II

Unified Symbol Framework to Improve UI Comprehension [slides.pdf]

Rentaro Yoshioka (University of Aizu), Naoyuki Murata (University of Aizu)

Smart Ontology-Based Event Identification [slides.pdf]

Sarika Jain (National Institute of Technology, Kurukshetra), Archana Patel (National Institute of Technology, Kurukshetra)

A Semi-Lossless Image Compression Procedure using a Lossless Mode of JPEG [slides.pdf]

Md. Atiqur Rahman (University of Aizu), Mohamed Hamada (University of Aizu)

Session 5-A: Interconnection Networks – I

A Low-Latency and Flexible TDM NoC for Strong Isolation in Security-Critical Systems [slides.pdf]

Miguel Gorgues Alonso (Universidad Politecnica de Valencia), José Flich (Universidad Politecnica de Valencia), Meriem Turki (University of Ferrara), Davide Bertozzi (University of Ferrara)

Low-Cost Congestion Detection Mechanism for Networks-on-Chip [slides.pdf]

Zhengqian Han (Waseda University), Michael Conrad Meyer (Waseda University), Xin Jiang (Kitakyushu College), Takahiro Watanabe (Waseda University)

A Machine Learning Enabled Long-Term Performance Evaluation Framework for NoCs [slides.pdf]

Jie Hou (University of Stuttgart), Qi Han (University of Stuttgart), Martin Radetzki (University of Stuttgart)

Fault-Tolerant Traffic-Aware Routing Algorithm for 3-D Photonic Networks-on-Chip [slides.pdf]

Michael Conrad Meyer (Waseda University), Yu Wang (The University of Aizu), Takahiro Watanabe (Waseda University)

Session 5-B: Intelligent Systems and Learning Technologies: Models, Methods, and Applications – II

Algorithm to Determine Extended Edit Distance between Program Codes [slides.pdf]

Kazuki Anzai (University of Aizu), Yutaka Watanobe (University of Aizu)

Automatic Generation of Fill-in-the-Blank Programming Problems [slides.pdf]

Kenta Terada (University of Aizu), Yutaka Watanobe (University of Aizu)

Convolutional Neural Network for Classification of Source Codes [slides.pdf]

Hiroki Ohashi (University of Aizu), Yutaka Watanobe (University of Aizu)

Design of Knowledge Templates and Multi-View Symbols for Experiential Learning [slides.pdf]

Takayuki Hoshino (University of Aizu), Rentaro Yoshioka (University of Aizu)

Session 6-A: Interconnection Networks – II

A Traffic-Robust Routing Algorithm for Network-on-Chip Systems [slides.pdf]

Siying Xu (Waseda University, Japan), Michael Conrad Meyer (Waseda University, Japan), Xin Jiang (Waseda University, Japan), Takahiro Watanabe (Waseda University, Japan)

Fault Detection and Localization for Network-on-Chips in Mixed-Criticality Systems [slides.pdf]

Adele Maleki (University of Siegen), Hamidreza Ahmadian (University of Siegen), Roman Obermaisser (University of Siegen)

An on-Communication Multiple-TSV Defects Detection and Localization for Real-Time 3D-ICs [slides.pdf]

Khanh N. Dang (Vietnam National University, Hanoi), Akram Ben Ahmed (Keio University), Xuan-Tu Tran (Vietnam National University, Hanoi)

A Hotspot-Pattern-Aware Routing Algorithm for Networks-on-Chip [slides.pdf]

Yaoying Luo (Waseda University, Japan), Michael Conrad Meyer (Waseda University, Japan), Xin Jiang (Waseda University, Japan), Takahiro Watanabe (Waseda University, Japan)

Session 6-B: Applications and Architectures designed for energy efficient hardware

Integrating Intra-and Intercellular Simulation of a 2D HL-1 Cardiac Model Based on Embedded GPUs [slides.pdf]

Baohua Liu (Shanghai University), Wenfeng Shen (Shanghai University), Xin Zhu (The University of Aizu), Xingyu Wangchen (Shanghai University)

Exploiting Model-Level Parallelism in Recurrent Neural Network Accelerators [slides.pdf]

Lu Peng (LSU), Wentao Shi (LSU), Jian Zhang (LSU), Samuel Irving (LSU)

Session 7-A: System Design

Towards an Efficient Hardware Architecture for Odd-Even Based Merge Sorter [slides.pdf]

Elsayed A. Elsayed (Tokyo Institute of Technology, Aswan University), Kenji Kise (Tokyo Institute of Technology)

Energy and Performance Analysis of STTRAM Caches for Mobile Applications [slides.pdf]

Kyle Kuan (University of Arizona), Tosiron Adegbija (University of Arizona)

Designing Application-Specific Heterogeneous Architectures from Performance Models [slides.pdf]

Thanh Cong (Univ Rennes, INRIA, CNRS, IRISA), François Charot (Univ Rennes, INRIA, CNRS, IRISA)

Efficient Search-Space Encoding for System-Level Design Space Exploration of Embedded Systems [slides.pdf]

Valentina Richthammer (Ulm University), Michael Glaß (Ulm University)

Session 7-B: Multicore/Manycore SoCs Programming

A Cloud Based Super-Optimization Method to Parallelize the Sequential Code’s Nested Loops [slides.pdf]

Amin Majd (Åbo Akademi University, Finland), Mohammad Loni (Mälardalen University, Sweden), Golnaz Sahebi (University of Turku, Finland), Masoud Daneshtalab (Mälardalen University, Sweden), Elena Troubitsyna (KTH Royal Institute of Technology, Sweden) 

Real-Time Implementation of Time-Space Continuous Dynamic Programming for Air-Drawn Character Recognition Using GPUs [slides.pdf]

Aki Nakamura (The University of Aizu), Yuichi Okuyama (The University of Aizu), Ryuichi Oka (The University of Aizu)

Session 8-A: Digital Circuit & FPGA-based Design – III

MITRACA: A Next-Gen Heterogeneous Architecture [slides.pdf]

Riadh Ben Abdelhamid (University of Tsukuba, Japan), Yoshiki Yamaguchi (University of Tsukuba, Japan), Taisuke Boku (University of Tsukuba, Japan)

A Preliminary Evaluation of Building Block Computing Systems [slides.pdf]

Sayaka Terashima (Keio University), Takuya Kojima (Keio University), Hayate Okuhara (Keio University), Kazusa Musha (Keio University), Hideharu Amano (Keio University), Ryuichi Sakamoto (The University of Tokyo), Masaaki Kondo (The University of Tokyo), Mitaro Namiki (Tokyo University of Agriculture and Technology)

Enhanced ID Authentication Scheme Using FPGA-Based Ring Oscillator PUF [slides.pdf]

Van-Toan Tran (Le Quy Don Technical University), Quang-Kien Trinh (Le Quy Don Technical University), Van-Phuc Hoang (Le Quy Don Technical University)

A STDM (Static Time Division Multiplexing) Switch on a Multi-FPGA System [slides.pdf]

Keita Azegami (Keio University), Kazusa Musha (Keio University), Kazuei Hironaka (Keio University), Akram Ben Ahmed (Keio University), Michihiro Koibuch (National Institute of Informatics), Yao Hu (National Institute of Informatics), Hideharu Amano (Keio University)

Session 8-B: Scalable and Flexible Many-Core Mapping and Runtime Techniques

Data-Driven Scenario-Based Application Mapping for Heterogeneous Many-Core Systems [slides.pdf]

Jan Spieck (Friedrich-Alexander-Universität Erlangen-Nürnberg), Stefan Wildermann (Friedrich-Alexander-Universität Erlangen-Nürnberg), Tobias Schwarzer (Friedrich-Alexander-Universität Erlangen-Nürnberg), Jürgen Teich (Friedrich-Alexander-Universität Erlangen-Nürnberg), Michael Glaß (Friedrich-Alexander-Universität Erlangen-Nürnberg)

Design-Time Memory Subsystem Optimization for Low-Power Multi-Core Embedded Systems [slides.pdf]

Manuel Strobel (University of Stuttgart), Martin Radetzki (University of Stuttgart)

Session 9: Reliable and Real-time Multicore/Manycore SoCs

A Real-Time Fault-Tolerant and Power-Efficient Multicore System on Chip [slides.pdf]

Alexander Gruzlikov (Concern CSRI Elektropribor, JSC), Nikolai Kolesov (Concern CSRI Elektropribor, JSC), Dmitrii Kostygov (Concern CSRI Elektropribor, JSC), Marina Tolmacheva (Concern CSRI Elektropribor, JSC)

Statistical Analysis for Shared Resources Effects with Multi-Core Real-Time Systems [slides.pdf]

Julien Durand (CPT), Youcef Bouchebaba (ONERA), Luca Santinelli (ONERA)

Lightweight Semantics-Preserving Communication for Real-Time Automotive Software [slides.pdf]

Eugene Yip (University of Bamberg, Germany), Erjola Lalo (Vector Informatik GmbH, Germany), Gerald Lüttgen (University of Bamberg, Germany), Andreas Sailer (Vector Informatik GmbH, Germany)