David Atienza , École Polytechnique Fédérale de Lausanne (EPFL), Switzerland
Towards Smart Wearable Systems in the Internet-of-Things Era
The evolution of semiconductor process technologies has enabled the miniaturization of sensors radio transceivers and computing platforms. This situation has made plausible to realize new low-cost wearable systems. However, the inherent resource-constrained nature of these systems, coupled with the harsh operating conditions and stringent autonomy requirements, pose important design challenges to make them provide automated and reliable analysis of complex biological signals. In addition, their increasing power requirements can result in degraded performance or a global energy crisis if they are massively deployed in the new era of Internet-of-Things (IoT). Therefore, this keynote addresses system-level design of next-generation smart wearable computing platforms. It first highlights the unsustainable energy cost incurred by the relatively straightforward wireless streaming of raw sensor data. Then, this talk advocates for a new system-level approach to synergistically design both hardware and software components of multi-processor system-on-chip (MPSoC) architectures that can be deployed ubiquitously, and provide real-time analysis of human bio-signals. This new MPSoC-based approach embeds more onboard intelligence and gracefully scales the energy consumption of next-generation smart wearable systems according to different operating requirements, by capitalizing on a better understanding how living organisms operate. Ultimately, this new proposed approach shows that the use of MPSoC-based wearable systems provides an ideal framework to develop ultra-low power detection and classification of human emotions from multiple bio-signals, which can then be used in wide variety of applications in the IoT era.
Biography: David Atienza received his MSc and PhD degrees in Computer Science and Engineering from UCM in Spain, and IMEC in Belgium in 2001 and 2005, respectively. Currently, he is Associate Professor of Electrical and Computer Engineering and Director of the Embedded Systems Laboratory (ESL) at EPFL, Switzerland. His research interests focus on system-level design methodologies for multi-core system-on-chip architectures (MPSoC) and embedded systems. In these fields, he is co-author of more than 200 publications, six US patents, and has received several best paper awards in top conferences. He received the IEEE CEDA Early Career Award in 2013, the ACM SIGDA Outstanding New Faculty Award in 2012 and a Faculty Award from Sun Labs at Oracle in 2011. He is a Distinguished Lecturer of IEEE CASS in 2014 and 2015. He was the Programme Chair of DATE 2015 and has been appointed as General Chair of DATE 2017. He is senior member of ACM and IEEE Fellow.
Benoît Dupont de Dinechin, Kalray, France
Engineering a Manycore Processor Platform for Mission-Critical Applications
Based on the experience of the Kalray MPPA-256 Bostan processor, we discuss the architectural and software tooling challenges of supporting mission-critical applications on a single-chip manycore processor. Mission-critical applications targeted by Kalray processors are found in defense, avionics, automotive, and large-scale physical instrumentation. Their key requirements are related to energy efficiency, functional safety and data security. Following an introduction to these applications and requirements, we put forward the proposed solutions. Energy efficiency is achieved by clustering large numbers of VLIW cores around multi-banked local memories. Timing predictability requirements are met through timing-compositional core micro-architecture, managed interference on the memory hierarchy components, and the configuration of the network-on-chip by network calculus. Dependability of software can be ensured by using model-based code generators such as SCADE Suite from Esterel Technologies. Finally, we present the main data security threats for these applications, and outline how they are addressed in current and next-generation processors.
Biography: Benoît Dupont de Dinechin is Chief Technology Officer of Kalray (http://www.kalray.eu), a company that manufactures integrated manycore processors for embedded and industrial applications. He is also the Kalray VLIW core main architect, and co-architect of the Kalray Multi Purpose Processing Array (MPPA). Before joining Kalray, Benoît was in charge of Research and Development of the STMicroelectronics Software, Tools, Services division, and was promoted to STMicroelectronics Fellow in 2008. Prior to STMicroelectronics, Benoît worked at the Cray Research park (Minnesota, USA), where he developed the software pipeliner of the Cray T3E production compilers. Benoît earned an engineering degree in Radar and Telecommunications from the Ecole Nationale Supérieure de l’Aéronautique et de l’Espace (Toulouse, France), and a doctoral degree in computer systems from the University Pierre et Marie Curie (Paris) under the direction of Prof. P. Feautrier. He completed his post-doctoral studies at the McGill university (Montreal, Canada) at the ACAPS laboratory led by Prof. G. R. Gao. Benoît has published over 50 conference papers, journal articles and book chapters, and holds 10 hardware patents.
Hoi-Jun Yoo, Korea Advanced Institute of Science and Technology (KAIST), South Korea
Brain-Inspired Intelligent SoCs and Applications
The intelligent SoCs inspired by the human brain will be introduced together with the AI hardware solutions. At first, the history of brain-mimicking SoCs will be reviewed from two perspectives; the low level neuron modeling and the high level AI. This dichotomy can be extended to mimic right-brain like “approximation and adaptation hardware” and left-brain like “precise and programmable Von Neumann architecture”. KAIST’s approach integrating both sides of brain will be explained. The deep neural networks and the specialized intelligent hardware (mimicking right brain) capable of statistical processing or learning and the multi-core processors (mimicking left brain) performing the precise computations including software AI are integrated on the same silicon chip. Especially, deep learning hardware will be introduced together with CNN (Convolutional Neural Network) and RNN (Recurrent Neural Network). Based on this brain-mimicking SoCs, the object recognition and the augmented reality applications are implemented with low-power and high-performance for wearable devices such as smart glasses, autonomous vehicles, and intelligent robots.
Biography: Hoi-Jun Yoo (M’95 – SM’04 – F’08) graduated from the Electronic Department of Seoul National University, Seoul, Korea, in 1983 and received the M.S. and Ph.D. degrees in electrical engineering from the Korea Advanced Institute of Science and Technology (KAIST), Daejeon, in 1985 and 1988, respectively. Since 1998, he has been the faculty of the Department of Electrical Engineering at KAIST and now is a full professor. From 2001 to 2005, he was the director of Korean System Integration and IP Authoring Research Center (SIPAC). From 2003 to 2005, he was the full time Advisor to Minister of Korea Ministry of Information and Communication and National Project Manager for SoC and Computer. In 2007, he founded System Design Innovation & Application Research Center (SDIA) at KAIST. Since 2010, he has served the general chair of Korean Institute of Next Generation Computing. His current interests are computer vision SoC, body area networks, biomedical devices and circuits. He is a co-author of DRAM Design (Korea: Hongrung, 1996), High Performance DRAM (Korea: Sigma, 1999), Future Memory: FRAM (Korea: Sigma, 2000), Networks on Chips (Morgan Kaufmann, 2006), Low-Power NoC for High-Performance SoC Design (CRC Press, 2008), Circuits at the Nanoscale (CRC Press, 2009), Embedded Memories for Nano-Scale VLSIs (Springer, 2009), Mobile 3D Graphics SoC from Algorithm to Chip (Wiley, 2010), Bio-Medical CMOS ICs (Springer, 2011), Embedded Systems (Wiley, 2012), and Ultra-Low-Power Short-Range Radios (Springer, 2015). Dr. Yoo received the Electronic Industrial Association of Korea Award for his contribution to DRAM technology in 1994, Hynix Development Award in 1995, the Korea Semiconductor Industry Association Award in 2002, Best Research of KAIST Award in 2007, Scientist/Engineer of this month Award from Ministry of Education, Science and Technology of Korea in 2010, Best Scholarship Awards of KAIST in 2011, and Order of Service Merit from Ministry of Public Administration and Security of Korea in 2011 and has been co-recipients of ASP-DAC Design Award 2001, Outstanding Design Awards of 2005, 2006, 2007, 2010, 2011, 2014 A-SSCC, Student Design Contest Award of 2007, 2008, 2010, 2011 DAC/ISSCC. He has served as a member of the executive committee of ISSCC, Symposium on VLSI, and A-SSCC and the TPC chair of the A-SSCC 2008 and ISWC 2010, IEEE Fellow, IEEE Distinguished Lecturer (’10-’11), Far East Chair of ISSCC (‘11-‘12), Technology Direction Sub-Committee Chair of ISSCC (’13), TPC Vice Chair of ISSCC (’14), and TPC Chair of ISSCC (’15).
Pascal Vivet, CEA-Leti, France
From 3D technology to 2.5D and 3D many-core architectures
With the era of massive multi-core architectures targeting cloud computing for high end performances or advanced consumer electronics with tighter power consumption constraints, 3D integration technology will allow to design and integrate large scale many-cores. 3D integration technology, using so called TSVs (Through Silicon Vias), is a natural evolution of packaging technologies. 3D technology offers further system integration using heterogeneous technologies, with already many different industrial successes (3D Imagers, 3D Mems, 2.5D Interposers, 3D DRAM Memory Cubes, etc.). Thanks to advanced 3D technology, it is possible to increase chip to chip communication bandwidth, maintain overall power consumption budget, and preserve overall system cost by smart system partitioning. Cea-Leti has been developing for a decade 3D integration, and have pursued research in both directions: developing advanced 3D technology bricks (TSVs, µ-bumps, Hybrid Bonding, etc), and designing advanced 3D circuits as pioneer prototypes. In this talk, it will be presented an introduction to 3D technology, an overview of Cea-Leti 3D technology and of recent 3D large scale many-core architectures. A dedicated focus will be given on the design of efficient 3D interconnect infrastructure, with 3D asynchronous Network-on-Chip architectures, with an overview on 3D CAD tools and associated challenges. Additional 3D technology evolutions and architecture possibilities will be presented, as further opportunities to design large scale many-cores using 3D technology.
Biography: Dr Pascal Vivet graduated from Telecom Bretagne, Brest and received his Master of Microelectronics from University Joseph Fourier (UJF), Grenoble in 1994. He accomplished his PhD in 2001 within France Telecom lab, Grenoble, designing an asynchronous Quasi-Delay-Insensitive microprocessor in the research group of Pr. Marc Renaudin. After 4 years within STMicroelectronics, Pascal Vivet has joined CEA-Leti in 2003 in the advanced design department of the Center for Innovation in Micro and Nanotechnology (MINATEC), Grenoble, France. His topics of interests are covering wide aspects from system level design and modeling, to asynchronous design, Network-on-Chip architecture, low power design, many core architectures, 3D design, including interactions with related CAD aspects. On 3D architecture, he strongly participates to the 3D design and roadmap within LISAN lab, with contributions on 3D asynchronous NoC, 3D Thermal modeling, 3D Design-for-Test, 3D physical design, and coordination of corresponding 3D CAD tools and CAD partners. Dr Pascal Vivet participates to various TPC such as ASYNC, NOCS, DATE, 3DIC, ICCAD conferences. He was general chair of ASYNC’10, and program chair of ASYNC’12. He participated actively as program chair or general chair to the 3D workshops at DATE since 2013, and to the D43D workshops since 2012. He is the author or co-author of a dozen of patents and of more than 80 papers.
Andreas Hansson, ARM,
Mind the gap
Today we have tremendous computing power at our fingertips. Highly-integrated Systems on Chip (SoCs) are enabled by continued scaling of semiconductor devices and state-of-the-art Intellectual Property (IP) blocks. These SoCs run elaborate software stacks and have multifaceted optimisation goals. As a result, evaluation and exploration is an increasingly complex task.
Work done in the research community does not currently align with these market trends, mostly due to the lack of appropriate methodologies and tools. The effort involved in system-level evaluation is simply perceived as too high. As a result, most academic works use ad hoc tools, consider IP blocks in isolation, and settle for simpler workloads and metrics.
In this talk, we demonstrate how openly-available frameworks enable hardware-software cross-layer optimisation and user-experience-aware design. We show how a more widespread community involvement allows us to close the gap.
Biography: Andreas Hansson is a strategic technical adviser at ARM, where he provides advice and assistance to the executive team, and leads a number of activities around technology exploration and incubation.
He holds an MSc degree from Lund Institute of Technology, Sweden, and a PhD degree from Eindhoven University of Technology, the Netherlands. His work has been published in numerous conferences and journals.