2027 MCSoC-NeuroCore Global Summit

The 2027 MCSoC–NeuroCore Global Summit is organized within the IEEE MCSoC Forum program and serves as a dedicated venue for advancing Neuromorphic Systems and Brain‑Inspired Computing. NeuroCore brings together leading researchers and practitioners to explore the principles, architectures, and technologies that enable intelligent computation grounded in neural and cognitive models. Its mission is to establish a rigorous foundation for devices, circuits, architectures, algorithms, and large‑scale systems that emulate the efficiency, adaptability, and parallelism of biological intelligence. As neuromorphic engineering expands across edge intelligence, autonomous systems, and emerging AI paradigms, NeuroCore provides a focused forum for breakthroughs that bridge neuroscience, computing, and next‑generation cognitive architectures—enabling scalable, energy‑efficient, and robust intelligent systems for real‑world deployment.

Program Chairs

Amirreza Yousefzadeh

University of Twente, The Netherlands

Xabier Iturbe

IK4-Ikerlan Research Alliance, Spain

Alberto Marchisio

New York University (NYU) Abu Dhabi, UAE

Topics of Interest

• Track1: Brain‑Inspired and Neuromorphic System Architectures
  Track Chair: Amirreza Yousefzadeh, University of Twente, The Netherlands
  • Brain-inspired computational primitives and network topologies.
  • System-level architectures combining neuromorphic and conventional cores.
  • Scalability and interconnect strategies for large neuromorphic systems.
  • Hierarchical and modular organization of neuromorphic architectures.
  • Cross-layer design linking neural models to system architecture.
• Track2: In‑Memory and Event‑Driven Computing Architectures
  Track Chair: TBC
  • Processing-in-memory and near-memory computing for neuromorphic workloads.
  • Event-driven and asynchronous dataflow architectures.
  • Memory technologies enabling in-situ computation.
  • Sparse and event-triggered data movement strategies.
  • Trade-offs between in-memory compute density and throughput.
• Track3: Architectures for Large‑Scale Spiking Neural Systems
  Track Chair: TBC
  • Scalable spiking neural network (SNN) hardware architectures.
  • Routing and communication fabrics for large-scale SNNs.
  • Hardware support for spike-based learning rules.
  • Synchronization and timing strategies across large spiking arrays.
  • Fault tolerance and reliability in large-scale SNN deployments.
• Track4: Neuromorphic Intelligence: Circuits, Systems, and Architectures
  Track Chair: Kaijie Wei, Keio University, Japan
  • Circuit-level innovations for neuromorphic intelligence.
  • Cross-layer system design from devices to architectures.
  • Integration of sensing, memory, and computation.
  • Analog and digital circuit co-design for neuromorphic intelligence.
  • System-level trade-offs between accuracy, latency, and power.
• Track5: Analog, Mixed‑Signal, and Memristive Neuromorphic Systems
  Track Chair: TBC
  • Analog and mixed-signal circuits for neuromorphic computation.
  • Memristive device integration for synaptic emulation.
  • Noise tolerance and variability mitigation in analog neuromorphic systems.
  • Calibration and compensation techniques for analog drift.
  • Hybrid analog-digital neuromorphic circuit design.
• Track6: Neuromorphic Approaches for Foundation Models and On‑Device AI
  Track Chair: TBC
  • Neuromorphic acceleration for foundation model inference.
  • Efficient on-device deployment of large models via spiking or event-driven methods.
  • Hybrid neuromorphic/conventional pipelines for edge AI.
  • Model compression and sparsification for neuromorphic deployment.
  • Latency and energy trade-offs for on-device foundation model inference.
• Track7: Simulation, Benchmarking, and Evaluation of Neuromorphic Systems
  Track Chair: TBC
  • Simulation frameworks and toolchains for neuromorphic hardware.
  • Benchmarking methodologies and standardized workloads.
  • Reproducibility and evaluation metrics for neuromorphic performance.
  • Cross-platform comparison of neuromorphic simulators and emulators.
  • Open datasets and benchmark suites for neuromorphic research.
• Track8: Energy‑Efficient Neuromorphic Accelerators for Edge and Cloud
  Track Chair: Farooq Khanday, University of Kashmir, India
  • Low-power neuromorphic accelerator design.
  • Energy-efficiency trade-offs across edge and cloud deployment.
  • Power management techniques for neuromorphic hardware.
  • Dynamic voltage and frequency scaling for neuromorphic accelerators.
  • Thermal and power budget constraints in deployment scenarios.
• Track9: Brain‑Inspired Algorithm–Hardware Co‑Optimization
  Track Chair: Alberto Marchisio, New York University Abu Dhabi, UAE
  • Joint optimization of learning algorithms and hardware constraints.
  • Hardware-aware training methods for neuromorphic systems.
  • Co-design methodologies bridging algorithms and circuits.
  • Quantization and precision-reduction strategies for neuromorphic learning.
  • Automated design-space exploration for algorithm–hardware pairs.
• Track10: Neuromorphic Approaches for Foundation Models and On‑Device AI
  Track Chair: TBC
  • Edge deployment strategies for foundation-model-derived workloads.
  • Neuromorphic techniques for continual and on-device learning.
  • Cross-domain applications combining neuromorphic and machine learning approaches.
  • Privacy-preserving on-device inference using neuromorphic methods.
  • Adaptation and personalization of models at the edge.
• Track11: Materials and Devices for Ultra‑Low‑Power Neuromorphic Systems
  Track Chair: TBC
  • Emerging materials for ultra-low-power synaptic and neuronal devices.
  • Device-level characterization and reliability studies.
  • Novel fabrication approaches for neuromorphic hardware.
  • Scaling limits and variability of emerging neuromorphic devices.
  • Integration pathways from device to system-level demonstration.
• Track12: Neuromorphic Software Stacks, Compilers, and Programming Models
  Track Chair: TBC
  • Compiler infrastructure for neuromorphic hardware targets.
  • Programming abstractions and frameworks for spiking systems.
  • Toolchains bridging high-level models and neuromorphic deployment.
  • Debugging, profiling, and visualization tools for neuromorphic software.
  • Interoperability standards across neuromorphic software stacks.
• Track13: Cognitive Computing Models and Brain‑Derived Algorithms
  Track Chair: Sichen Tao, Tohoku University, Japan
  • Computational models inspired by cognitive and neural processes.
  • Brain-derived algorithms for perception and decision-making.
  • Cognitive architectures for adaptive intelligent systems.
  • Models of attention, memory, and learning inspired by neuroscience.
  • Evaluation of cognitive models against biological plausibility.
• Track14: Brain‑Inspired Hardware for Cognitive and Adaptive Systems
  Track Chair: Khanh Dang, The University of Aizu, Japan
  • Hardware platforms supporting cognitive-level processing.
  • Adaptive and self-organizing neuromorphic hardware.
  • Integration of cognitive models into embedded hardware.
  • On-chip learning and plasticity mechanisms for adaptive systems.
  • Real-time cognitive processing under resource constraints.
• Track15: Novel Devices for Neuromorphic Computing: Memristors, PCM, RRAM
  Track Chair: Xumeng Zhang, Fudan University, China
  • Memristor, PCM, and RRAM device physics for neuromorphic applications.
  • Synaptic and neuronal emulation using emerging non-volatile devices.
  • Reliability, endurance, and scalability of novel neuromorphic devices.
  • Multi-level and analog switching behavior in emerging devices.
  • Array-level integration and yield considerations.
• Track16: 3D Integrated and Heterogeneous Neuromorphic Systems
  Track Chair: Xabier Iturbe, IK4-Ikerlan Research Alliance, Spain
  • 3D integration techniques for neuromorphic system stacking.
  • Heterogeneous integration of neuromorphic and conventional compute layers.
  • Thermal and interconnect challenges in 3D neuromorphic systems.
  • Chiplet-based approaches to heterogeneous neuromorphic integration.
  • Vertical interconnect and through-silicon-via strategies for 3D stacks.

Proceedings Publication and Indexing

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The conference proceedings, including all technical tracks, special tracks, and special sessions and workshop papers, will be published by IEEE Conference Proceedings, which will be included in the Computer Society Digital Library (CSDL) and IEEE Xplore, subject to meeting IEEE Xplore’s scope and quality requirements.

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