Special Session: Low-power and Solutions for Future SoC design



Nowadays, Systems-on-Chips (SoCs) are increasingly hosting several processors, memories, and custom modules to satisfy the different performance requirements in high-performance and embedded applications. The increase in the number of cores and the shrinkage in the chip size has made power consumption one of the ultimate design challenges in such SoCs. The urge to further reduce the power consumption of SoCs has become more critical with the emergence of new technologies that mainly target reduced power consumption rather than working at high frequencies. Low-power processors have been required for various Internet of Things (IoT) systems and Neural Computing. The need for low-power solutions for future SoC designs has become primordial. This special session solicits contributions related to contemporary architectures, techniques, and methodologies for efficient low-power SoC designs. Topics of interest include, but are not limited to:

  • Low-power digital architectures include power-efficient memory/cache designs, interconnections, and microarchitectures.
  • Ultra-low-power chip prototyping of digital VLSI systems
  • Green High-performance computing
  • CAD tools and methodologies related to low-power design include power optimizations, reliability impacts on power consumption, and power modeling.
  • Energy-efficient software and applications, including OS power scheduling and management

Former Chairs:

Prof. Hayate Okuhara, National University of Singapore, Singapore  (16th IEEE MCSoC 2023)