Special Session: Low-power and Solutions for Future SoC design

Organizer/Chair

Akram Ben Ahmed, (Information Technology Research Institute, AIST, Japan)

Hayate Okuhara,(National University of Singapore, Singapore )

Nowadays, Systems-on-Chips (SoCs) are increasingly hosting several processors, memories, and custom modules to satisfy the different performance requirements in high-performance and embedded applications. The increase in the number of cores, in addition to the shrinkage in the chip size, has made power consumption one of the ultimate design challenges in such SoCs. The urge to further reduce the power consumption of SoCs has become more important with the
emergence of new technologies that mainly target reduced power consumption rather than working at high frequencies. In fact, low-power processors have been required for various Internet of Things (IoT) systems, as well as Neural Computing. The need for low-power solutions for future SoC designs has become primordial. This special session is dedicated to presenting the recent architectures, techniques, and methodologies for efficient low-power SoC designs. Topics of interest include, but are not limited to:

  • Low-power digital architectures such as power-efficient memory/cache designs,
  • interconnections and micro architectures.
  • Ultra low power chip prototyping of digital VLSI systems
  • Green High-performance computing
  • CAD tools and methodologies related to low power design such as power optimizations,
  • reliability impacts on power consumption, and power modeling.
  • Energy efficient software and applications including OS power scheduling and
  • management.

Paper Submission

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Reviewers

TBC