The IEEE MCSoC Forum is a premier global flagship event sponsored by IEEE and the IEEE Computer Society (TCMM). It unites researchers, practitioners, and industry experts working in embedded system design, multicore and many‑core architectures, embodied AI platforms, neuromorphic and brain‑inspired computing systems, and integrated circuit design for emerging and next‑generation applications.
The 19th IEEE MCSoC 2026 will be held in Shanghai, China, from December 14–17, 2026. Evolving from its origins in parallel and heterogeneous computing, this edition will address critical challenges in multicore systems, focusing strongly on innovations in embedded AI and machine learning.
The robust technical program will feature keynote lectures, special sessions, and 19 specialized tracks. Key topics include heterogeneous architectures, energy-efficient computing, NoC technologies, neuromorphic systems, and chiplet-based integration. Building on a rich legacy of global editions across Asia, Europe, and the Americas, MCSoC 2026 continues to foster interdisciplinary collaboration and drive the future of intelligent multicore systems.
Hybrid Format: MCSoC 2026 will support both in‑person attendance and online participation, ensuring broad accessibility for the global community.
All papers must follow the official double‑column IEEE conference format and be submitted in PDF only. Regular papers may include up to 8 pages, with an additional charge of 50 USD per extra page (maximum of 2 extra pages). Short papers are strictly limited to 4 pages, and no extra pages are permitted. Authors are strongly encouraged to ensure that their manuscripts are properly formatted, clearly written, and free of typographical or grammatical errors before submission.
Presentation‑Only submissions are reviewed for relevance and quality but are not included in the proceedings and do not produce an archival publication. Accepted presentation‑only work will appear in the conference program and program booklet and will receive a presentation slot during the event.
All submissions will undergo a single‑blind peer‑review process conducted by at least three qualified reviewers. Each paper will be evaluated based on its technical quality, originality, significance of the contribution, clarity of presentation, and overall organization. Reviewers may also consider the relevance of the work to the conference themes and the soundness of the methodology. Papers that do not meet the formatting requirements or fall short of expected academic standards may be rejected without full review.
Paper Submission & Deadlines
Requirements
- Regular Paper: Max 8 pages
- Short Paper: Max 4 pages
- Double-column IEEE format
- Format: PDF Only
Important Dates
- Submission:
April 30, 2026 –> May 31–> June 20 (CLOSED) - Notification: July 20, 2026
- Camera-Ready & Author Registration:
July 31, 2026–> August 5, 2026 - Event: Dec 14-17, 2026
Technical Tracks
- Programming Techniques for Embedded Multicore/Manycore SoCs
Focus: Parallel programming models, compiler support, and software optimization. - Architectural Innovations in Embedded Multicore/Manycore SoCs
Focus: Novel core designs, memory hierarchies, and scalable architectures. - Design Methodologies for Embedded Multicore/Manycore SoCs
Focus: System-level design, modeling, and co-design strategies. - Heterogeneous Integration and Advanced On-Chip Interconnects
Focus: NoC architectures, routing algorithms, and communication-aware design. - Testing, Security, and Trust in Embedded Multicore/Manycore Systems
Focus: Hardware security, fault tolerance, and trust verification. - Design Automation and Low-Power Techniques for Embedded Manycore SoCs
Focus: CAD tools, power-aware synthesis, and energy-efficient design flows. - Real-Time Systems for Embedded Multicore/Manycore SoCs
Focus: Scheduling, timing analysis, and predictability. - Operating System Platforms for Real-Time Embedded Applications
Focus: RTOS design, virtualization, and OS-level support.
- Hardware Acceleration of AI on Embedded Edge SoCs
Focus: AI inference engines, edge deployment, and hardware-software co-design. - Machine Learning for Energy-Efficient and Reliable Manycore Systems
Focus: ML-based optimization, reliability modeling, and performance tuning. - Chiplet-Based Architectures and Design for Multicore SoCs
Focus: Modular integration, inter-chip communication, and scalable ecosystems. - Sustainable Design and Lifecycle Management for Multicore SoCs
Focus: Carbon-aware computing, energy harvesting, and recyclable materials. - Privacy-Preserving AI Acceleration on Embedded Multicore SoCs
Focus: Federated learning, homomorphic encryption, and trusted execution environments. - Multicore SoCs for Cyber-Physical and Autonomous Systems
Focus: Sensor fusion, control loops, safety-critical systems, and edge autonomy. - Application Domains for Embedded Multicore/Manycore SoCs
Focus: Automotive, robotics, healthcare, and industrial use cases. - Quantum and Hybrid Classical-Quantum Computing SoCs
Focus: Quantum algorithms, QML acceleration, and hybrid classical-quantum hardware/software co-design.
MCSoC Global Summits
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2026 MCSoC‑NeuroCore Global Summit on Neuromorphic Systems and Brain‑Inspired Computing
Focus: Neuromorphic Engineering; Cognitive Architectures; SNNs; Edge Intelligence. -
2026 MCSoC‑EmbodiCore Global Summit on Embodied AI and Distributed Autonomous Systems
Focus: Embodied AI, Distributed Autonomy, and Intelligent Physical Systems.
Special Sessions
Proceedings Publication and Indexing
Indexed by
Published in
The conference proceedings, including all technical tracks, special tracks, special sessions, and workshop papers, will be published by IEEE Conference Proceedings. These will be included in the Computer Society Digital Library (CSDL) and IEEE Xplore, subject to meeting IEEE Xplore’s scope and quality requirements.
