Track Chair
TBC
The rapid growth of AI, edge intelligence, and neuromorphic computing is pushing conventional monolithic CMOS architectures to their limits. The von Neumann bottleneck—long the dominant constraint on compute efficiency—now stands as the primary obstacle to achieving brain‑like parallelism and ultra‑low‑power processing. To overcome this barrier, the community is accelerating toward heterogeneous integration, 3D architectures, and next‑generation on‑chip interconnect technologies that tightly couple compute, memory, and emerging device modalities.
This track invites original contributions that explore the architectures, materials, packaging technologies, and circuit innovations enabling the next wave of high‑performance, energy‑efficient, and cognitively inspired systems.
Topics of Interest (include but are not limited to):
1. 3D Integration and Multi‑Modal Packaging
- 3D chiplets, 2.5D/3D packaging, and advanced heterogeneous integration
- EMIB, Foveros, hybrid bonding, and wafer‑level stacking
- Thermal, mechanical, and reliability challenges in deep 3D stacks
- Co‑design methodologies for multi‑modal integration (compute, memory, sensing)
2. Advanced On‑Chip Interconnects
- Scalable 2D/3D Networks‑on‑Chip (NoCs) for many‑core and neuromorphic systems
- Photonic‑electronic interconnects and silicon photonics for high‑bandwidth, low‑latency communication
- Interconnect‑aware mapping, routing, and power optimization
- Fault‑tolerant and reliability‑driven interconnect architectures
3. Emerging Memory and Synaptic Devices
- Memristive, spintronic, ferroelectric, and phase‑change synapses
- Two‑terminal memristors and three‑terminal neuromorphic transistors
- Device‑circuit co‑design for in‑memory and near‑memory computing
- Variability, endurance, and scaling challenges in emerging NVM technologies
4. Neuromorphic and AI‑Centric Heterogeneous Architectures
- Integration of neuromorphic cores with digital logic and accelerators
- Multi‑modal compute substrates combining CMOS, RRAM, MRAM, PCM, and spintronics
- Event‑driven, massively parallel architectures inspired by biological computation
- Cross‑layer design for ultra‑low‑power AI and edge intelligence
5. Tools, Models, and Design Methodologies
- CAD/EDA tools for 3D integration and heterogeneous packaging
- Modeling of thermal, electrical, and reliability behavior in stacked systems
- System‑level simulation frameworks for heterogeneous SoCs
- AI‑driven optimization for interconnect and packaging design
Submission Guidelines
Authors are invited to submit original, unpublished research manuscripts that align with the themes of this track. Submissions will undergo rigorous peer review based on technical quality, novelty, and relevance.
Former Chairs
- Prof. Baris Taskin, Drexel University, U.S.A. (2025)
- Prof. José L. Abellán, University of Murcia, Spain ( 2023 , 2024 )
