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Dr. Kiat Seng Yeo, Professor, Advisor (Global Partnerships) at Singapore University of Technology and Design (SUTD), Singapore
Title: Can Modern Electronics Keep Pace with Moore’s Law?
Abstract: The invention of the transistor in 1948 at Bell Laboratories was a turning point in the history of electronics. The transistor promises to revolutionize electronics; indeed, it has become an integral and essential part of our lives. This talk begins with an introduction to early computers, the invention of integrated circuits, and how it changed the electronics industry. As integrated circuits evolve, it is essential to know the forces that have driven it along its historical trajectory and to discover how much further it could go. Can the electronic revolution keep pace with Moore’s Law? What are the embedded system design and technology challenges? Is electronics still evolving, or has it come to an end? What is the next big thing? How is it going to affect us? This keynote will attempt to answer these questions. In conclusion, the other trends to watch for the next revolution will be presented.
Biography: Professor Kiat Seng YEO (M’00–SM’09–F’16) received his B.Eng. (EE) in 1993 and Ph.D. (EE) in 1996, both from Nanyang Technological University (NTU), Singapore. Currently, he is a full professor and Advisor (Global Partnerships) at the Singapore University of Technology and Design (SUTD) and a distinguished professor at Tianjin University. He was Chairman of the University Research Board, Member of the Academic Council, Associate Provost for Research, and Founding Associate Provost for Graduate Studies and International Relations at SUTD. He has over 30 years of experience in industry, academia, and consultancy. Before joining SUTD, he was a full professor at NTU; and spent 13 years in management positions as Associate Chair (Research), Head of Circuits and Systems, and Sub-Dean (Students Affairs). Professor Yeo was also a Fellow of the Renaissance Engineering Programme (REP) and was a Senator and Advisory Board Member at NTU. He has made many outstanding contributions to advance Singapore’s education and research ambitions throughout his career. As the Founding Director of VIRTUS, a S$52 million IC Design Centre of Excellence jointly set up by NTU and the Singapore Economic Development Board (EDB), he contributed extensively to the economic development of integrated circuit design in Singapore by leading multidisciplinary research, with a focus on industry collaboration. In 2016, he initiated the FIRST (Fostering Industrial Research Success Together) Industry Workshop at SUTD. Today, it is a flagship event with an attendance of over 1,000 professionals from the industry. Since 1996, Professor Yeo has been providing consultancy services to statutory boards, local SMEs, and multinational corporations in the areas of electronics and IC design. As Principal Investigator, he secured over SGD70 million in research funding from various funding agencies and industry. He is the author of 13 books and 7 book chapters and has published over 600 top-tier refereed journal and conference papers in his area of research and holds 39 patents, including 2 patents for the world’s smallest integrated transformer, a patent for the world’s smallest integrated filter for 60GHz standard, the inventor of several high Q-factor RF spiral inductors and co-inventor of quite a few novel circuit techniques for 5G/6G wireless communication and RF/mm-wave IC applications. Professor Yeo is a world-renowned expert in low-power RF/mm-wave integrated circuit design and a recognized expert in CMOS technology. He holds/held positions such as advisor, chair, co-chair, and technical chair at many international conferences. He was awarded the Public Administration Medal (Bronze Award) by the President of the Republic of Singapore on National Day 2009 and was awarded the Nanyang Alumni Achievement Award in 2009 in recognition of his outstanding contributions to the University and society. Professor Yeo is an academician of the Singapore Academy of Engineering, an academician of the Singapore National Academy of Science, a Fellow of IEEE, and a Fellow of the Asia-Pacific Association for Artificial Intelligence (AAIA). He is the principal author of the Integrated Circuit Design Research Ranking for Worldwide Universities 2008 and World University Research Rankings (WURR) 2020. Professor Yeo was ranked among the World’s top 2% of scientists by Stanford University from 2020 to 2023.
Dr. Yuichi Nakamura, Senior Executive Professional, NEC Corp, Japan / Guest Professor, Waseda University, Japan
Title: Quantum Computing: New Frontier or Nightmare?
Abstract: Quantum computers would be able to perform calculations in a few seconds which would take conventional computers millions of years, and there are great expectations regarding their high speed. For example, a Quantum Computer has the potential to discover new medicine and the composition of new catalysts that contribute to carbon neutrality by its high-speed calculation. Quantum computers have also the potential to generate up to trillions of dollars in value through efficiency improvements in finance, transportation, factory automation, and machine learning. In this talk. the basics and calculation principles of quantum computer calculations are presented, and then the technical issues facing the practical application of quantum computers, and the possibilities for solving the causes are explained.
Biography: Dr. Yuichi Nakamura received his B.E. in information engineering and M.E. in electrical engineering from the Tokyo Institute of Technology in 1986 and 1988, respectively. He received his Ph.D. from the Graduate School of Information, Production and Systems, Waseda University, in 2007. He joined NEC Corp. in 1988 and led NEC’s research about embedded system design and quantum technologies as a general manager and a vice president at NEC research and development. Currently, he is a senior executive professional at NEC Corp. He is also a guest professor at Kyushu University, Waseda University, and Tokyo University and an invited professor at Osaka University. He has over 30 years of professional experience
in electronic design automation, signal processing, supercomputer design, combinational optimization, and quantum computing. Dr. Yuichi Nakamura contributed to managing and leading several innovative signal processing and computing projects. He has published over 25 journal articles and 40 international conference papers and has had many keynote talks at major conferences. He is a board member of the Japanese government quantum innovation meeting, a program officer of the Japanese Quantum sensing project, and an evaluation committee of several Japanese government grant meetings.
Dr. Ahmed Fakhfakh, General Director of the Digital Research Center of Sfax (CRNS) / Professor, National School of Electronics and Telecommunications of Sfax (ENET’Com), Sfax, Tunisia
Title: Real-Time High-Precision Indoor Mobile Target Localization Using Energy-Efficient Wireless Sensor Networks
Abstract: Indoor localization of a mobile target represents a prominent application within a wireless sensor network (WSN), showcasing significant values and scientific interest. Interference, obstacles, and energy consumption are critical challenges for indoor applications and battery replacements. A proposed tracking system deals with several factors, such as latency, energy consumption, and accuracy, presenting an innovative solution for the mobile localization application. This study investigates various methods and algorithms for real-time localization of a mobile object within a confined indoor environment, aiming to achieve the highest possible accuracy while minimizing energy consumption. We utilized a wireless sensor network (WSN) to gather and process localization data. Our comprehensive evaluation encompassed state-of-the-art signal processing techniques, machine learning algorithms, and hybrid approaches integrating multiple data sources. The primary focus was optimizing the trade-off between localization precision and energy efficiency, addressing challenges such as signal interference, environmental variability, and computational constraints. Experimental results demonstrate that the proposed methods significantly enhance real-time localization accuracy and reduce power consumption, providing valuable insights for developing energy-efficient indoor positioning systems utilizing WSNs.
Biography: Ahmed Fakhfakh has been a full professor at the National School of Electronics and Telecommunications of Sfax (ENET’Com) at the University of Sfax in Tunisia since 2015 and the General Director of the Digital Research Center of Sfax (CRNS) since 2023. He obtained his HDR diploma from Sfax University in 2009, his PhD from Bordeaux University, France, in 2002, and his electrical engineering diploma in 1997 from Sfax National School of Engineering (ENIS), Tunisia. He is the head of the Intelligent Systems: Design and Implementation research group at the Laboratory of Signals, SysteMs, aRtificial Intelligence and neTworkS (SM@RTS) in the digital research centre of Sfax in Tunisia. His research interests include developing smart solutions for energy management in a smart grid, designing and implementing IoT solutions, designing wake-up solutions for Wireless sensor network applications, and designing energy harvesting solutions.
Dr. Hiroki Nakahara, CEO, Tokyo Artisan Intelligence Co., Ltd. / Professor, Tohoku University, Japan
Title: An FPGA-based Accelerator Platform for an Edge AI
Abstract: With the development of deep learning, the “edge AI” market, including embedded systems, tends to expand. Since edge AI requires
large operations under limited computational resources, data structures, and architectures are being researched and developed. The importance of edge AI is increasing due to security and communication speed considerations, and its applications are expanding. However, edge AI requires lightweight models and hardware innovations to process in real-time due to limited computational resources. We will introduce technologies suitable for edge AI. Prof. Hiroki Nakahara established Tokyo Artisan Intelligence (TAI) Co., Ltd., which develops edge AI for business. We will introduce the edge AI business conducted at TAI and the SEASIDE (A Specified Edge AI SoM for Intelligence Design and Embedding) platform, an edge AI solution by TAI. SEASIDE is an FPGA-based computation platform, enabling the efficient implementation of AI solutions that customize models by leveraging the
flexibility of the FPGA. This presentation will explain TAI FPGA implementation technology and introduce the roadmap for the SEASIDE platform.
Biography: Hiroki Nakahara is a founder and CEO at Tokyo Artisan Intelligence Co., Ltd., a professor at Tohoku University, and a specific professor at
Tokyo Insitute of Technology. His research interests include logic synthesis, reconfigurable architecture, embedded systems, and machine learning. He received a Ph.D. degree in computer science from the Kyushu Institute of Technology in 2007. Prof. Nakahara received the 8th IEEE/ACM MEMOCODE Design Contest 1st Place Award in 2010, the SASIMI Outstanding Paper Award in 2010, the IPSJ Yamashita SIG Research Award in 2011, the 11th FIT Funai Best Paper Award in 2012, the 7th IEEE MCSoC-13 Best Paper Award in 2013, and the ISMVL2013 Kenneth C. Smith Early Career Award in 2014. He was the Workshop Chairman for the ULSIWS from 2014 to 2017; as the Program Chairman for the HEART in 2017. In addition, due to his academic contributions, he was selected as the general chair of the FPT’23. In 2022, the National Institute for Science and Technology Policy (NISTEP) awarded him the title of “Nice Step Researchers 2022” for his outstanding contributions to the development of science, technology, and innovation.
Mr. Yong Kai Ping, Chief Executive Officer of the Selangor Information Technology & Digital Economy Corporation (Sidec), Malaysia
Title: Malaysia Semiconductor IC Design Park Development: Pioneering Southeast Asia’s Semiconductor Future
Abstract: As Southeast Asia rises to prominence in the global semiconductor industry, Malaysia stands at the forefront with its groundbreaking initiative, the Malaysia Semiconductor IC Design Park. This keynote session, delivered by Yong Kai Ping, CEO of SIDEC, will explore the strategic vision behind this transformative project, its role in positioning Malaysia as a regional leader, and its impact on the global semiconductor landscape. The session will delve into how the IC Design Park, supported by the collaboration of federal and state governments, global technology firms, and venture capitalists, is creating an ecosystem that fosters innovation, talent development, and sustainable growth. The park is designed to attract cutting-edge IC design companies, offering advanced infrastructure, Electronic Design Automation (EDA) tools, and critical industry partnerships. Yong Kai Ping will highlight key milestones of the initiative, including the role of the Malaysia Advance Semiconductor and AI Academy in training the next generation of engineers, and the establishment of the RM100 million Semiconductor Venture Fund, which aims to fuel the growth of high-potential semiconductor companies in Malaysia. Join this keynote to gain insight into how Malaysia is pioneering the future of semiconductors in Southeast Asia and laying the groundwork for a new era of technological leadership in the region.
Biography: Yong Kai Ping is the esteemed Chief Executive Officer of the Selangor Information Technology & Digital Economy Corporation (Sidec). With a robust background in digital transformation and media, Yong has been instrumental in positioning Selangor as ASEAN’s leading digital hub. His strategic leadership at Sidec focuses on accelerating digitalization across e-commerce, startups, and SMEs, fostering an ecosystem of innovation and growth. Yong’s journey in the digital economy is marked by his notable tenure as CEO of Sidec since 2021 and as CEO of SITEC from 2015 to 2020. Under his guidance, SITEC significantly contributed over RM334 million to the Selangor economy and nurtured 90 startups through the Selangor Accelerator Programme. Yong’s visionary efforts have facilitated the digital education of 650 e-commerce merchants and successfully promoted SME digitalization. Before leading Sidec and SITEC, Yong was at the helm of KiniTV as its CEO, where he propelled the platform to achieve 150 million views in 2015, establishing it as one of Southeast Asia’s largest online TV channels. His extensive experience includes a pivotal role as the Chinese Editor for Malaysiakini, Malaysia’s most influential online news portal, where he served for nearly 12 years. A British Chevening Scholar, Yong holds a Master of Arts in International Relations from the University of Birmingham, UK. He has further enriched his expertise through participation in the Senior Journalist Programme at the East West Centre in Hawaii, USA. He has organized prominent media conferences, including the Asia Chinese New Media Conference and the Southeast Asia Internet TV Conference. Yong’s accolades include the Digital Hub Status award by MDEC and Silicon Valley Pitching & Industrial Visit. His dedication to the digital economy and media has propelled his professional success and significantly impacted Selangor’s economic landscape, making him a distinguished leader in the field.
Takahiro Hanyu , Professor, Tohoku University, Japan
Title: ”Challenge of MTJ-Based Nonvolatile Hardware for Edge AI Applications ”
Abstract: Nonvolatile spintronic devices have potential advantages such as fast read/write and high endurance together with back-end-of-the-line compatibility of semiconductor fabrication, which offers the possibility of constructing not only stand-alone RAMs and embedded RAMs that can be used in conventional VLSI circuits and systems but also realizing standby-power-free and high-performance VLSI processors, which could open up a practical intermittent-computing paradigm for internet-of-things (IoT) applications. My presentation presents some AI-hardware examples based on MTJ-based nonvolatile logic-in-memory architecture, and their suitability for IoT applications is discussed.
Biography: Takahiro Hanyu received the B.E., M.E., and D.E. degrees in Electronic Engineering from Tohoku University, Sendai, Japan, in 1984, 1986, and 1989, respectively. He is currently a full professor and the director (from April 2022 to present) at the Research Institute of Electrical Communication, Tohoku University. His general research interests include nonvolatile logic circuits, their applications to ultra-low-power and/or highly dependable VLSI processors and post-binary computing, and their application to brain-inspired VLSI systems and edge AI hardware.
He received the Sakai Memorial Award from the Information Processing Society of Japan in 2000, the Judge’s Special Award at the 9th LSI Design of the Year from the Semiconductor Industry News of Japan in 2002, the Special Feature Award at the University LSI Design Contest from ASP-DAC in 2007, the APEX Paper Award of Japan Society of Applied Physics in 2009, the Excellent Paper Award of IEICE, Japan, in 2010, the Ichimura Academic Award in 2010, the Best Paper Award of IEEE ISVLSI 2010, the Paper Award of SSDM 2012, the Best Paper Finalist of IEEE ASYNC 2014, and the Commendation for Science and Technology by MEXT, Japan, in 2015. Dr. Hanyu is a Senior Member of the IEEE.
Mahdi Nikdast, Associate Professor, Colorado State University, USA
Title: ”The Silicon Photonics Marathon: From Optical Interconnect to Computing and Memory!”
Abstract: Silicon photonics technology has facilitated the deployment of integrated photonics across different application domains, from ultra-fast communication for chip-scale interconnect and Datacom applications to energy-efficient optical computation for accelerating AI and machine learning applications. More recently, the integration of silicon photonics and nonvolatile phase change materials has also created a unique opportunity to realize photonic memory and in-memory optical computing. In this keynote, through an interdisciplinary approach and from device to system level, I will present a holistic overview of the promise and challenges of silicon photonics when employed for inter- and intra-chip optical interconnect AI acceleration and memory applications. I will present several examples of many-core systems-on-chip (SoCs) integrating silicon photonics and how to design solutions based on hardware-software co-design and cross-layer co-optimization that can efficiently address some of the existing challenges in such systems.
Biography: Mahdi Nikdast is an Associate Professor and Endowed Rockwell-Anderson Professor in the Department of Electrical and Computer Engineering at Colorado State University (CSU), Fort Collins, where he is directing the Electronic-PhotoniC System Design (ECSyD) Laboratory. He received his Ph.D. in Electronic and Computer Engineering from The Hong Kong University of Science and Technology (HKUST), Hong Kong, in 2014. From 2014 to 2017, he was a postdoctoral fellow at McGill University and Polytechnique Montreal, Quebec, Canada. His research interests are at the intersection of integrated photonics, emerging technologies, and high-performance computing. Prof. Nikdast and his students have published numerous papers in refereed journals and international conference publications and across different areas of VLSI, EDA, Photonics, Embedded Systems, Systems-on-Chip (SoCs), Artificial Intelligence (AI), and Computer Architecture. He has edited a book on Silicon Photonics for High-Performance Computing and Beyond, published by Taylor and Francis Group in 2022, and another book on Photonic Interconnects for Computing Systems: Understanding and Pushing Design Challenges, published by River Publishers in 2017. Prof. Nikdast currently serves as an Associate Editor for IEEE Transactions on Very Large Scale Integration Systems (IEEE TVLSI), and has served on the TPC of various international conferences, including DAC, OFC, DATE, ICCAD, ESWEEK, NOCS, etc. He is a co-founder of the International Workshop on Optical/Photonic Interconnects for Computing Systems (OPTICS workshop) and the North American Workshop on Silicon Photonics for High-Performance Computing (SPHPC Workshop). Prof. Nikdast and his team were the recipient of various awards, including the Second Best Project Award at the AMD Technical Forum and Exhibition (AMD-TFE 2010, Taiwan), the Best Paper Award at the Asia Communications and Photonics Conference (ACP 2015, Hong Kong), the Best Paper Award at the Design, Automation, and Test in Europe (DATE) Conference (DATE 2016 – Test Track, Dresden), the Best Paper Award Candidate at ACM Great Lake Symposium on VLSI (GLSVLSI 2018, USA), and the Best Paper Honorable Mention Award at ACM Great Lake Symposium on VLSI (GLSVLSI 2020, China). Prof. Nikdast received the prestigious NSF CAREER Award (2021), the George T. Abell Award for Outstanding Early-Career Faculty (2022), the Rockwell-Anderson Professorship (2022), and the George T. Abell Award for Teaching and Mentoring (2023). He is a Senior Member of the IEEE.
Khein-Seng Pua, Founder and CEO of Phison Electronics, Taiwan
Title: ”Challenges and Opportunities of Next-Generation Enterprise SSD Storage”
Abstract: Data is driving the transformation of the world, including the Internet of Everything, AI, and high-speed computing technologies. All of which are driving the digital transformation of all industries and assisting humans and enterprises to make faster and more accurate decisions through data analysis and artificial intelligence. In such a transformation process, data storage and reading and writing behaviors play a very important role; for example, the computing results of artificial intelligence come from the collection of big data, the foundation of cloud services comes from the construction of data centers, and the server environment for high-speed computing comes from the matching stable and high-speed enterprise-level storage architecture. What kind of challenges and opportunities will enterprise SSDs face due to the transformation of these digital technologies? Welcome to the keynote speech of KSPua, CEO of Phison, to explore the latest enterprise SSD technologies and development trends.
Biography: KS Pua is the Founder and CEO of Phison Electronics. He was born in a farming community Sekinchan in Selangor, Malaysia, in 1974. At the age of 19, he went to Taiwan with just US$4,000 in his pocket. With no relatives to help him, his only dream was to study hard; he graduated from National Chiao Tung University (NCTU) in Hsinchu, Taiwan, in 1997 and earned a Master’s from NCTU in 1999. Mr. Pua and his four friends founded Phison Electronics Corp. in Taiwan. He designed and produced the world’s first single-chip USB flash controller with other founders. Under his leadership, the company has become a global leader in NAND Flash controller IC and storage solutions. As an entrepreneur, Mr. Pua is a successful high-tech entrepreneur and the recipient of the Ten Outstanding Young Malaysian Awards and received the Outstanding Young Entrepreneur Award, the Outstanding Young Manager Award, and The President Award of National Management Excellence Award from the Government. He was elected a Fellow of the Chinese Society for Management Of Technology in 2009. In 2020, Phison enjoyed a turnover of US$1.64 billion and became the largest independent NAND controller and NAND storage solution provider globally, and was named 65th in U.S magazine Bloomberg Businessweek’s Tech 100 in the year of 2010. From 2015 to the present, the production value of Phison was ranked top 4 IC Design Houses in Taiwan’s IC design industry.
Steven Fong, Managing Director, AMD South Asia Pacific Sales, Singapore
Title: ”Accelerating Silicon technology to deliver the exponential growth in Compute”
Abstract: As we migrate up the use case on vast data collected globally over decades, the need for computing grows to manage that transition. There is a huge implication for the accelerated push on silicon technology to deliver that compute level. With Moore’s law diminishing after decades of keeping up the double in 2 years, this poses an exponential challenge to deliver the desired compute in a silicon device. The industry needs to innovate to compensate for the decelerating Moore law. One of the changes that allow us to keep up is Advanced packaging, which has grown in importance to the performance of the device. Using 2D, 2.5D, 3D with better TSV, interposer, and interconnect will soon become the next norm. Another emerging side effect of expanding computing is the need for power and thermal management. With the infinite number of connected devices over the next decades, the semiconductor industry has an impact on world energy. This raises the importance of performance per watt, especially from the recent impact of Generative AI on data centers.
Biography: Steven Fong is Managing Director for AMD South Asia Pacific Sales since the merger of AMD/Xilinx. Prior, he spent 11 years (2008-2022) with Xilinx across multiple roles as Senior Director. Steven had established the Global Pricing group and was managing both Xilinx worldwide strategic and field tactical pricing. Several world-class business models are now intrinsic to AMD Adaptive Embedded Computing Group’s commercial principles. The newly built pricing establishment has become an essential cornerstone to enable Xilinx’s world-class growing Gross margin from 2009 (GM 64%) to 2019 (GM 73%). Steven also doubled his role to establish Xilinx worldwide first consumer strategy (2014~2016) and is a sitting member of AMD Singapore leadership council till now. Steven founded Xilinx South Asia Pacific Sales Group (2019) and doubled the business over three years. Prior to Xilinx, Steven spent 13 years in STMicroelectronics as a regional & global marketing/business leader for Analog products. He established STMicroelectronic first Asian-based Global strategic business unit in 2004 and doubled the revenue/margin over four years. Steven graduated with an honor degree (Electronic Engineering, 1995) from Nanyang Technological University. He also has a Master in Management (2006) from the Macquarie Graduate School of Management, an MBA (2008) from the University of Western Australia, and a Postgraduate Diploma from the Chartered Institute of Marketing (UK).
Jerald Yoo, National University of Singapore, Singapore.
Title: ”On-Chip Epilepsy Detection: Where Machine Learning Meets Patient-Specific Wearable Healthcare”
Abstract: Epilepsy is a severe and chronic neurological disorder that affects over 65 million people worldwide. Yet current seizure/epilepsy detection and treatment mainly rely on a physician interviewing the subject, which is not effective in the infant/children group. Moreover, patient-to-patient and age-to-age variation in seizure patterns from surface EEG makes such detection particularly challenging. To expand the beneficiary group to include even infants and also to effectively adapt to each patient, a wearable form factor, the patient-specific system with machine learning is crucial. However, the wearable environment is challenging for circuit designers due toan unstable skin-electrode interface, large mismatch, and tatic/dynamic offset. This talk will cover the design strategies of a patient-specific epilepsy detection System-on-Chip (SoC). We will first explore the difficulties, limitations, and potential pitfalls in wearable interface circuit design and approaches to overcome such issues. We will cover various IA circuit topologies and their key metrics to deal with offset compensation. Several state-of-the-art instrumentation amplifiers that emphasize different parameters will also be discussed. Moving on, we will explore the feature extraction and the patient-specific classification using the Machine Learning technique. Comparison of different algorithms under limited training sets will be made. Finally, an on-chip epilepsy detection and recording SoC will be presented, which integrates all the components covered during the talk. The talk will conclude with interesting aspects and opportunities that lie ahead. Biography Jerald Yoo received the B.S., M.S., and Ph.D. degrees in the Department of Electrical Engineering from the Korea Advanced Institute of science and Technology (KAIST), Daejeon, Korea, in 2002, 2007, and 2010, respectively. From 2010 to 2016, he was with the Department of Electrical Engineering and Computer Science, Masdar Institute, Abu Dhabi, United Arab Emirates, where he was an Associate Professor. from 2010 to 2011, he was also with the Microsystems Technology Laboratories (MTL), Massachusetts Institute of Technology (MIT) as a visiting scholar. Since 2017, he has been affiliated with the Department of Electrical and Computer Engineering at the National University of Singapore, Singapore, where he currently serves as an Associate Professor. He has pioneered research on low-energy body-area-network (BAN) transceivers and wearable body sensor networks using the planar-fashionable circuit board for a continuous health monitoring system. He authored book chapters in Biomedical CMOS ICs (Springer, 2010) and in Enabling the Internet of Things—From Circuits to Networks (Springer, 2017). His current research interests include low-energy circuit technology for wearable bio-signal sensors, flexible circuit board platform, BAN transceivers, ASIC for piezoelectric Micromachined Ultrasonic Transducers (pMUT) and System-on-Chip (SoC) design to system realization for wearable healthcare applications. Dr. Yoo served as an IEEE Circuits and Systems Society (CASS) Distinguished Lecturer from 2019 to 2021, as well as an IEEE Solid-State Circuits Society (SSCS) Distinguished Lecturer from 2017 to 2018. He is the recipient or a co-recipient of several awards: IEEE International Solid-State Circuits Conference (ISSCC) 2020 Demonstration Session Award (Certificate of Recognition), IEEE International Symposium on Circuits and Systems (ISCAS) 2015 Best Paper Award (BioCAS Track), ISCAS 2015 Runner-Up Best Student Paper Award, the Masdar Institute Best Research Award in 2015, and the IEEE Asian Solid-State Circuits Conference (A-SSCC) Outstanding Design Award (2005). He was the founding vice-chair of the IEEE SSCS United Arab Emirates (UAE) Chapter and is currently the chair of the IEEE SSCS Singapore Chapter. Currently, he serves as a Technical Program Committee Member of the IEEE International Solid-State Circuits Conference (ISSCC), co-chair of the ISSCC Student Research Preview, and Chair of the Emerging Technologies and Applications Subcommittee at the IEEE Asian Solid-State Circuits Conference (A-SSCC). He also served as the subcommittee chair at the IEEE Custom Integrated Circuits Conference (CICC). He is
also an Analog Signal Processing Technical Committee Member of IEEE Circuits and Systems Society, and an Associate Editor of IEEE Transactions on Biomedical Circuits and Systems as well as IEEE Open Journal of Solid-State Circuits Society (OJ-SSCS). He is a senior member of IEEE
Amine Bermak, Hamad Bin Khalifa University (HBKU), Qatar
Title: From Wearable Sensors to IoT Microsystems
Abstract: This talk will present enabling technologies for IoT sensing, addressing key issues related to power consumption, energy harvesting, and calibration of “autonomous Microsystems”. We will first outline how wearable sensors are currently being deployed for many IoT applications and present the future prospects of wearable sensors. Three case studies will be presented, namely: (i) smart vision systems with energy harvesting capabilities, (ii) Batteryless temperature sensing for passive RFID applications, and (iii) olfactory sensors with self-calibration capability. The talk will cover state-of-the-art technological developments in this area and will outline existing challenges as well as emerging new opportunities for research and innovation in this rapidly growing field. The conclusion of the talk will discuss whether autonomous microsystems, including wearable sensors, are becoming a reality or are just another engineering dream idea.
Bibliography: Prof. Amine Bermak received the master’s and PhD degrees, both in electrical and electronic engineering, from Paul Sabatier University, Toulouse, France, in 1994 and 1998, respectively. He has held many positions in various continents, including a full Professor at HKUST, Hong Kong, a Senior lecturer at Edith Cowan University, Australia, and a Post-doc at York University, England, in a project funded by British Aerospace. He is currently a Professor and Associate Dean at the College of Science and Engineering, Hamad Bin Khalifa University, Qatar. Prof. Bermak is the recipient of 5 best papers awards and the winner of the 2011 Michael G. Gale Medal for distinguished teaching at HKUST and the “Engineering School Teaching Excellence Award”. He is the recipient of the Best Researcher Award at CSE in 2019. Prof. Bermak has published over 350 articles in journals, book chapters, and conference proceedings, and has designed more than 50 chips. He has supervised 35 PhD and 16 MPhil students. He has served on the editorial board of IEEE Transactions on Very Large Scale Integration (VLSI) Systems, IEEE Transactions on Circuits and Systems II, IEEE Transactions on Biomedical Circuits and Systems, IEEE Transactions on Electron Devices, and Nature Scientific Reports. Prof. Bermak was the co-director of the MIT-HKUST Consortium. He is an IEEE Distinguished Lecturer and a Fellow of IEEE.
2012
Dr. Fumio ARAKAWA, Chief Professional, Renesas Electronics Corp., Japan
 Trend of Multi-/Many-core for Embedded Systems A multi-/many-core is one of the most promising approaches to realize high-efficiency, which is the key factor to achieve high-performance under some fixed power and cost budgets. A cloud system enables thin clients in many cases relying on high-performance of severs remotely connected by network; however, it is still desirable to accomplish a real-time or dependable operation locally by an embedded system. This is because some critical operation does not allow slow or unpredictable response caused by network delay or disconnection. Such a disadvantage of network should be concealed from a user. Therefore, embedded systems will employ multi-/many-core architecture more and more to realize various cool functionalities with/without network. A heterogeneous multi-core chip, RP-X integrates eight SH-X4 CPU cores, four flexible engine (FE) cores, two matrix processor (MX) cores, and a video processing unit (VPU). The SH-X4 cores run at 648MHz and achieve totally 13.7 Dhrystone GIPS and 36.3 peak GFLOPS. Overall, the RP-X achieves 114.7GOPS with 3.07W, and the power-performance ratio is as high as 37.3 GOPS/W. Biography: Fumio Arakawa is a chief professional in the System Core Development Division of Renesas Electronics. His research interests include architecture and micro-architecture of low-power and high-performance microprocessors. Arakawa has a PhD in electrical engineering from the University of Tokyo. He’s a program committee co-chair of the Cool Chips conference series, a guest editor of COOL Chips Special Section/Issue of IEEE Micro, a program committee member of the VLSI Circuits Symposium, and the chairman of Microprocessor Technical Committee and Multi-/Many-core Application Research Committee of Japan Electronics and Information Technology Industries Association. He’s a member of IEEE and IEICE. Dr. Luca BENIN, Professor, University of Bologna, Italy  Scalable Many-core Acceleration for Image Understanding – is CPU+GPU the answer? Image understanding is becoming the next “killer app” for mobile and embedded platforms and devices. Visual search, face and gesture recognition, SLAM, 3D reconstruction are computationally intensive and complex algorithms which will have to run in real-time with a very modest power budget in next-generation smart phones, tablets, TVs… The hunt for the best computational engine for image understanding is now open. Some serious contenders are already emerging, high-frequency SMP-style embedded CPUs and GP-GPUs being the main ones. In this talk I would discuss the pros and cons of these architectures in running image understanding applications, and I will give my view and experience in designing an alternative scalable computational fabric to hit the sweet spot in terms of GOPS/mm2/W while preserving a standard-based software API for ecosystem build-up and application integration. Biography: Luca Benini is Full Professor at the Department of Electrical Engineering and Computer Science (DEIS)of the University of Bologna, Italy. He also holds a visiting faculty position at the Ecole Polytechnique Federale de Lausanne (EPFL) and he is currently serving as Chief Architect for the Platform 2012 project in STmicroelectronics, Grenoble. He received a Ph.D. degree in electrical engineering from Stanford University in 1997. Dr. Benini’s research interests are in energy-efficient system design and Multi-Core SoC design. He is also active in the area of energy-efficient smart sensors and sensor networks for biomedical and ambient intelligence applications. He has published more than 500 papers in peer-reviewed international journals and conferences, four books and several book chapters. He has been the general chair and program chair of the Design Automation and Test in Europe Conference. He has been a member of the technical program committee and organizing committee of several conferences, including the Design Automation Conference, the International Symposium on Low Power Design, the Symposium on Hardware-Software Codesign. He has been Associate Editor of several international journals, including the IEEE Transactions on Computer Aided Design of Circuits and Systems and the ACM Transactions on Embedded Computing Systems. He is a Fellow of the IEEE, a member of the Academia Europaea, and a member of the steering board of the ARTEMISIA European Association on Advanced Research & Technology for Embedded Intelligence and Systems. Dr. Sofiène TAHAR, Professor, Concordia University, Montreal, Canada  System-on-Chip Design Verification: Challenges and State-of-the-art We address an important area of System-on-Chip R&D activity, namely “Design Verification”. Verification today is known to cost about 70% of industrial electronics design projects, in terms of human, computer and budget. Many product delays are caused by verification taking longer than expected, and despite multiple efforts, products are delivered with uncaught bugs. We present the different kinds of verifications used today in an industrial design flow, namely design, implementation and fabrication verification. We then focus more on design verification from high level specification to gate-level implementation. Several technologies will be displayed and compared, drawing a picture to still open problems and possible research issues. Among them, “formal verification” is one of the most active areas that is carried out recently and which make use of computerized mathematical reasoning to verify system properties. Example applications of this technology used in industry scale projects will be presented and discussed. Biography: Sofiene Tahar received in 1990 the Diploma degree in computer engineering from the University of Darmstadt, Germany, and in 1994 the Ph.D. degree with “Distinction” in computer science from the University of Karlsruhe, Germany. Currently he is Professor in the Department of Electrical and Computer Engineering at Concordia University, Montreal, Quebec, Canada, where he is holding a Senior Research Chair in Formal Verification of System-on-Chip. Prof. Tahar is founder and director of the Hardware Verification Group at Concordia University, which focuses on developing verification technologies in the fields of microelectronics, telecommunications, security, aviation, etc. He has received several awards and distinctions, including in 2010 a National Discovery Award, given to Canada’s top 100 researchers in engineering and natural sciences. Prof. Tahar is a senior member of IEEE and member of the Order of Engineers of Quebec, ACM, IEEE Computer and IEEE Communications Societies. Dr. Hideharu AMANO, Professor, Keio University, Japan  An NoC Architecture for Inductive Coupling Wireless Interconnect The initial cost of LSI for design and mask is growing in advanced technologies, and developing various types of SoC (System-on-a-Chip)s for required application has become difficult. SiP (System in Package) or 3-dimensional implementation techniques can address the problem by connecting multiple dies. Various scales and functions can be realized from various combination of dies. Especially, inductive coupling wireless 3-D connection is attractive because of its flexibility. An NoC architecture which enables to replace and add dies is proposed. By using a simple ring topology and bubble-flow control, dies can be connected and switched without deadlock. The experience using a prototype chip Cube-0 is reported. Biography: Hideharu Amano received the Ph.D degree from Keio University, Japan in 1986. He is now a Professor in the Department of Information and Computer Science, Keio University. His research interests include the area of parallel architectures and reconfigurable computing. Dr. Yukoh MATSUMOTO, President, TOPS Systems Corp., Japan  Cool System: A Scalable and Energy-Efficient 3D Heterogeneous Multi-Chip System with Cool Interconnect, Cool Chip, and Cool Software “Smart” Information Systems, such as next-generation Smart Phones, Tablets, Smart-TVs, Automotive safety systems, etc. drive evolution of SoC architecture to meet these system requirements such as high performance with scalability and flexibility of functionality, with low- power and low-cost in short time-to-market, that currently limited by SOCs integrating multiple processor cores and a number of hardwired accelerator IPs. 3-D Multi-Chip stacking is a promising technology to overcome the “memory wall”, “power wall”, “ILP wall”, and “utilization wall”. In this presentation, I introduce a vision and architecture of Cool System that consists of three fundamental technologies, such as 1) Cool Chip, to make a high performance microprocessor chip to be low-power enough to avoid heat issue, 2) Cool Software, to increase processor core utilization with distributed processing software, and 3) Cool Interconnect, to enable low-power and scalable 3D Multi-Chip stacking of heterogeneous LSIs. Cool System architecture takes an approach to drastically reduce the operating clock frequency, but keep the high performance with several hardware-software techniques and optimizations through architecture-and-algorithm co-design. 1) Cool Chip architecture has features such as, a heterogeneous Multi-Core with stream processing cores, distributed parallel processing with zero-overhead message passing mechanisms, application domain specific heterogeneous Multi-Core configurations in Instruction Set Architecture and , etc. 2) Cool Software is a distributed parallel processing software based on Kahn Process Network Model with stream processing scheduling. 3) Cool Interconnect is a common interface to enable scalable and heterogeneous multi-chip stacking with low-power, wide bandwidth communication. Example application domains, such as next generation DTV and Video Mining, and their domain-specific architectural solutions will be presented. In addition, the architectural details and characteristics of the Cool Interconnect test chip and Cool System test chips will be presented. Biography: Dr. Yukoh Matsumoto is the chief architect, president, and CEO of TOPS Systems Corp. He led “Cool System: Ultra-Low-Power 3D stacked heterogeneous Multicore / Multichip” project, supported by NEDO and the “Ultra-Android: Distributed Processing embedded software platform” project, supported by METI. Currently, he is working on the “Low-Power Many-Core Architecture and Compiler Technology” project supported by NEDO. In his 26 years of career, he has architected and designed over 10 advanced microprocessors such as Embedded Multicore processors, x86 microprocessors, and DSPs. He founded TOPS Systems Corp. in 1999 and received the Takeda Techno-Entrepreneurship Award, Tsukuba Venture Award, and ET Award in hardware in 2001, 2010, and 2011, respectively. Prior to TOPS Systems, he had held several positions within Texas Instruments and its R&D organization in the US and Japan, and V.M. Technology, a microprocessor start-up in Japan. He received the Doctor of Information Sciences (Ph.D.) degree from the Graduate School of Tohoku University, Sendai, Japan, in 2007, and participated in the MOT (Management of Technology) program at the Graduate School of Engineering in Tokyo University from 2004 through 2005. He is also President & CEO of Cool Soft Corp., and a member of the Microprocessor Technical Committee, Multi/Many-core Application Research Committee, Information System Disruptive Technology Research Committee, and 3D Semiconductor Sub-Committee of JEITA. |
