The exponential increase in complexity and integration density of embedded multicore and manycore systems has created unprecedented challenges in ensuring their dependability. As these systems are increasingly deployed in safety-critical domains—such as automotive, aerospace, and medical infrastructure—the cost of failure or security breaches becomes unacceptable. This track addresses the intersection of reliability, security, and hardware trust. It explores innovative methodologies to detect manufacturing defects in nanometer-scale technologies, protect shared resources from side-channel attacks, and ensure long-term reliability against aging and soft errors. We invite researchers to submit contributions that advance the state-of-the-art in design-for-testability (DfT), hardware security primitives, and resilient system architectures.
Topics of Interest
We welcome submissions related, but not limited, to the following areas:
Advanced Testing & Design for Testability (DfT)
- Automatic Test Pattern Generation (ATPG) & Test Compression
- Design for Testability (DfT) for SoC, NoC, ASIC, and 3D-ICs
- Built-In Self-Test (BIST) and Online/In-Field Testing
- Memory Test, Diagnosis, and Repair (BISR)
- Testing for Analog, Mixed-Signal, and RF Circuits
- Delay Fault Modeling, Diagnosis, and Failure Analysis
Hardware Security & Trust
- Design for Security and Hardware Trustworthiness
- Detection of Hardware Trojans and Counterfeit ICs
- Side-Channel Attacks and Countermeasures
- Secure Boot, Physical Unclonable Functions (PUFs), and TRNGs
- Cyberattack Defense in Embedded Hardware
- Security Verification and Validation
Reliability, Safety & Fault Tolerance
- Reliability Awareness, Prediction, and Aging Modeling
- Fault Tolerance, Error Detection, Correction, and Recovery (EDAC)
- Self-Repair, Restructuring, and Reconfiguration Mechanisms
- Functional Safety and ISO 26262 Compliance for Automotive ICs
- Soft Error Analysis and Radiation Hardening
Emerging Domains & Adaptive Systems
- Testing and Reliability of Machine Learning (ML) Accelerators
- Adaptive Embedded Hardware Architectures and Design
- Test Synthesis and Fault Simulation for Adaptive Systems
- Security and Trust in FPGA-based and Reconfigurable Systems
Former Chairs
- Zheng Yue, The Chinese University of Hong Kong, Shenzhen, China (MCSoC 2025)
- Tanja Harbaum, Karlsruhe Institute of Technology (KIT), Germany (17th IEEE MCSoC 2024)
- Yeong-Kang Lai, NCHU, Taiwan (16th IEEE MCSoC 2023)
